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JPS5694646A - Forming method for oxidized film - Google Patents

Forming method for oxidized film

Info

Publication number
JPS5694646A
JPS5694646A JP17037379A JP17037379A JPS5694646A JP S5694646 A JPS5694646 A JP S5694646A JP 17037379 A JP17037379 A JP 17037379A JP 17037379 A JP17037379 A JP 17037379A JP S5694646 A JPS5694646 A JP S5694646A
Authority
JP
Japan
Prior art keywords
groove
si3n4
flat surface
width
resist
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17037379A
Other languages
Japanese (ja)
Inventor
Koichi Kobayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP17037379A priority Critical patent/JPS5694646A/en
Publication of JPS5694646A publication Critical patent/JPS5694646A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
    • H01L21/76208—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region using auxiliary pillars in the recessed region, e.g. to form LOCOS over extended areas

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)
  • Element Separation (AREA)
  • Formation Of Insulating Films (AREA)
  • Local Oxidation Of Silicon (AREA)

Abstract

PURPOSE:To obtain the oxidized film having a flat surface by preparing an etching groove vertical to an Si substrate, together with an Si3N4 film, by using a resist mask provided adjacently with small holes or narrow grooves, and by subjecting the same to thermal oxidation. CONSTITUTION:The thin Si3N4 film 2 is provided on the Si substrate 1 and the resist mask 3 is applied thereto. Resist width Wp is slightly larger than groove width Ws. Next, when Si3N4 and Si are etched through reactive spatter etching, lateral etching is not caused, while the groove sufficiently deep compared with the width Ws is formed vertically. When the resist is removed and the thermal oxidation is applied, SiO2 grows from both sides of the groove 4 and fills up the groove. Si3N4 being removed finally, an SiO2 layer having the flat surface is obtained. By this method, the thick oxidized film can be obtained in a short time and further a highly-precise insulation-substance layer having the flat surface and being fitted for minute elements can be obtained.
JP17037379A 1979-12-28 1979-12-28 Forming method for oxidized film Pending JPS5694646A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17037379A JPS5694646A (en) 1979-12-28 1979-12-28 Forming method for oxidized film

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17037379A JPS5694646A (en) 1979-12-28 1979-12-28 Forming method for oxidized film

Publications (1)

Publication Number Publication Date
JPS5694646A true JPS5694646A (en) 1981-07-31

Family

ID=15903725

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17037379A Pending JPS5694646A (en) 1979-12-28 1979-12-28 Forming method for oxidized film

Country Status (1)

Country Link
JP (1) JPS5694646A (en)

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3715092A1 (en) * 1986-05-09 1987-11-12 Seiko Epson Corp METHOD FOR PRODUCING A SEMICONDUCTOR ARRANGEMENT
US4927784A (en) * 1987-05-01 1990-05-22 Raytheon Company Simultaneous formation of via hole and tube structures for GaAs monolithic microwave integrated circuits
US5374583A (en) * 1994-05-24 1994-12-20 United Microelectronic Corporation Technology for local oxidation of silicon
US5395790A (en) * 1994-05-11 1995-03-07 United Microelectronics Corp. Stress-free isolation layer
US5472903A (en) * 1994-05-24 1995-12-05 United Microelectronics Corp. Isolation technology for sub-micron devices
EP0996149A1 (en) * 1998-10-23 2000-04-26 STMicroelectronics S.r.l. Manufacturing method for an oxide layer having high thickness
US6599812B1 (en) 1998-10-23 2003-07-29 Stmicroelectronics S.R.L. Manufacturing method for a thick oxide layer
US6869856B2 (en) 2001-10-30 2005-03-22 Stmicroelectronics S.R.L. Process for manufacturing a semiconductor wafer integrating electronic devices including a structure for electromagnetic decoupling
JP2006100825A (en) * 2004-09-29 2006-04-13 Agere Systems Inc Thick oxide region in semiconductor device and its forming method
EP1702358A2 (en) * 2003-12-19 2006-09-20 Third Dimension (3D) Semiconductor, Inc. A method for forming thick dielectric regions using etched trenches
JP2007129116A (en) * 2005-11-07 2007-05-24 Tokyo Electron Ltd Method and device for manufacturing semiconductor device, control program and computer recording medium
JP2008153685A (en) * 2001-05-18 2008-07-03 Fuji Electric Device Technology Co Ltd Manufacturing method of semiconductor device

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3715092A1 (en) * 1986-05-09 1987-11-12 Seiko Epson Corp METHOD FOR PRODUCING A SEMICONDUCTOR ARRANGEMENT
US4927784A (en) * 1987-05-01 1990-05-22 Raytheon Company Simultaneous formation of via hole and tube structures for GaAs monolithic microwave integrated circuits
US5395790A (en) * 1994-05-11 1995-03-07 United Microelectronics Corp. Stress-free isolation layer
US5374583A (en) * 1994-05-24 1994-12-20 United Microelectronic Corporation Technology for local oxidation of silicon
US5472903A (en) * 1994-05-24 1995-12-05 United Microelectronics Corp. Isolation technology for sub-micron devices
US6599812B1 (en) 1998-10-23 2003-07-29 Stmicroelectronics S.R.L. Manufacturing method for a thick oxide layer
EP0996149A1 (en) * 1998-10-23 2000-04-26 STMicroelectronics S.r.l. Manufacturing method for an oxide layer having high thickness
JP2008153685A (en) * 2001-05-18 2008-07-03 Fuji Electric Device Technology Co Ltd Manufacturing method of semiconductor device
US6869856B2 (en) 2001-10-30 2005-03-22 Stmicroelectronics S.R.L. Process for manufacturing a semiconductor wafer integrating electronic devices including a structure for electromagnetic decoupling
EP1702358A2 (en) * 2003-12-19 2006-09-20 Third Dimension (3D) Semiconductor, Inc. A method for forming thick dielectric regions using etched trenches
EP1702358A4 (en) * 2003-12-19 2008-07-02 Third Dimension 3D Sc Inc PROCESS FOR FORMING THICK DIELECTRIC REGIONS USING SERIOUS TRENCHES
JP2006100825A (en) * 2004-09-29 2006-04-13 Agere Systems Inc Thick oxide region in semiconductor device and its forming method
JP2007129116A (en) * 2005-11-07 2007-05-24 Tokyo Electron Ltd Method and device for manufacturing semiconductor device, control program and computer recording medium

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