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JPS5690336A - Circuit adapter apparatus - Google Patents

Circuit adapter apparatus

Info

Publication number
JPS5690336A
JPS5690336A JP16858379A JP16858379A JPS5690336A JP S5690336 A JPS5690336 A JP S5690336A JP 16858379 A JP16858379 A JP 16858379A JP 16858379 A JP16858379 A JP 16858379A JP S5690336 A JPS5690336 A JP S5690336A
Authority
JP
Japan
Prior art keywords
information
circuit
terminal equipment
display
receiving signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16858379A
Other languages
Japanese (ja)
Inventor
Hiroshi Hayashi
Kiyoshi Oi
Takiko Fuji
Sadao Fukatsu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP16858379A priority Critical patent/JPS5690336A/en
Publication of JPS5690336A publication Critical patent/JPS5690336A/en
Pending legal-status Critical Current

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  • Computer And Data Communications (AREA)

Abstract

PURPOSE: To obtain the desired information among the information existing in an electronic computer side, by a terminal equipment, by reading out the information designated by the terminal equipment, from the memory of the electronic computer, and constituting so that said information can be transmitted to the terminal equipment.
CONSTITUTION: The receiving circuit 7 receives a display request signal which is sent from the terminal equipment, and it is transferred to the receiving signal analytic circuit 8. The circuit 8 analyzes the receiving signal under the condition that the circuit adapter for CPU is nonbusy, reads out the status information of the kind which is designated by the receiving signal, and commands to the display information generating circuit 9 that said information is to be transmitted. The circuit 9 accesses the memory of the CPU in accordance with the command from the circuit 8, edits the read-out data to a suitable format, and transmits the edited display information to the terminal equipment. When this display information is received, the terminal equipment displays it on the display picture.
COPYRIGHT: (C)1981,JPO&Japio
JP16858379A 1979-12-25 1979-12-25 Circuit adapter apparatus Pending JPS5690336A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16858379A JPS5690336A (en) 1979-12-25 1979-12-25 Circuit adapter apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16858379A JPS5690336A (en) 1979-12-25 1979-12-25 Circuit adapter apparatus

Publications (1)

Publication Number Publication Date
JPS5690336A true JPS5690336A (en) 1981-07-22

Family

ID=15870740

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16858379A Pending JPS5690336A (en) 1979-12-25 1979-12-25 Circuit adapter apparatus

Country Status (1)

Country Link
JP (1) JPS5690336A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5831464A (en) * 1981-08-19 1983-02-24 Fujitsu Ltd Transmission system of job output information

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5831464A (en) * 1981-08-19 1983-02-24 Fujitsu Ltd Transmission system of job output information
JPS6244666B2 (en) * 1981-08-19 1987-09-22 Fujitsu Ltd

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