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JPS5678155A - Semiconductor device and manufacture thereof - Google Patents

Semiconductor device and manufacture thereof

Info

Publication number
JPS5678155A
JPS5678155A JP15518879A JP15518879A JPS5678155A JP S5678155 A JPS5678155 A JP S5678155A JP 15518879 A JP15518879 A JP 15518879A JP 15518879 A JP15518879 A JP 15518879A JP S5678155 A JPS5678155 A JP S5678155A
Authority
JP
Japan
Prior art keywords
layer
film
opening
multicrystal
type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15518879A
Other languages
Japanese (ja)
Inventor
Takahiro Okabe
Tomoyuki Watabe
Toru Nakamura
Kenji Kaneko
Yutaka Okada
Minoru Nagata
Masao Tamura
Hiroshi Tamura
Nobuyoshi Kashu
Takashi Tokuyama
Yasuo Wada
Osamu Minato
Shinya Oba
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP15518879A priority Critical patent/JPS5678155A/en
Publication of JPS5678155A publication Critical patent/JPS5678155A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation

Landscapes

  • Physics & Mathematics (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Optics & Photonics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Electromagnetism (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Bipolar Transistors (AREA)
  • Bipolar Integrated Circuits (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

PURPOSE:To obtain an element which has a less parasitic capacity, by a method wherein an insulation film is adhered onto a semiconductor substrate, an opening is formed for growing an Si layer thereat, a laser annealing process is performed after a single crystal layer is formed in the opening and a multicrystal layer on the film, and said layer are laminated in a manner described above. CONSTITUTION:An SiO2 film 2 is adhered onto a type N Si substrate 1, and an opening is formed at a given region for growing a type P impurity matter on the whole surface. After a multicrystal Si layer 6 and a type P single crystal Si layer 5 are formed on the film 2 and on the exposed substrate 1 in the opening, respectively, in a condition to be connected together, a laser annealing process takes place. Said layer are then etched to form a given shape, and are covered with an SiO2 film 7. An opening 8 is formed in the layer 6, and Si including a type N impurity matter is caused to grow on the whole surface. A signal crystal layer 9 and a multicrystal layer are formed on the layer 6 and on the film 7, respectively, and the laser annealing process takes place. Afterwards, the layer 9 is hot-etched to form a desired shape, and the whole surface is covered with an SiO2 film 10 whereat openings are formed. Electrodes 12 and 11 are then adhered to a part 61 of the exposed layer 6 and to a multicrystal layer 91 connected to the layer 9, respectively.
JP15518879A 1979-11-30 1979-11-30 Semiconductor device and manufacture thereof Pending JPS5678155A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15518879A JPS5678155A (en) 1979-11-30 1979-11-30 Semiconductor device and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15518879A JPS5678155A (en) 1979-11-30 1979-11-30 Semiconductor device and manufacture thereof

Publications (1)

Publication Number Publication Date
JPS5678155A true JPS5678155A (en) 1981-06-26

Family

ID=15600403

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15518879A Pending JPS5678155A (en) 1979-11-30 1979-11-30 Semiconductor device and manufacture thereof

Country Status (1)

Country Link
JP (1) JPS5678155A (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS587869A (en) * 1981-07-07 1983-01-17 Nec Corp Semiconductor device
JPS5833869A (en) * 1981-08-25 1983-02-28 Toshiba Corp Semiconductor device
JPS5837953A (en) * 1981-08-31 1983-03-05 Toshiba Corp Laminated semiconductor integrated circuit device
JPS5853821A (en) * 1981-09-25 1983-03-30 Toshiba Corp Preparation of laminated semiconductor device
JPS5856362A (en) * 1981-09-29 1983-04-04 Fujitsu Ltd Manufacturing method of semiconductor device
JPS5893225A (en) * 1981-11-30 1983-06-02 Toshiba Corp Preparation of semiconductor thin film structure
JPS59182570A (en) * 1983-03-31 1984-10-17 Fujitsu Ltd semiconductor equipment
JPS60189217A (en) * 1984-03-09 1985-09-26 Agency Of Ind Science & Technol Seed structure for multilayer SOI

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS587869A (en) * 1981-07-07 1983-01-17 Nec Corp Semiconductor device
JPS5833869A (en) * 1981-08-25 1983-02-28 Toshiba Corp Semiconductor device
JPS5837953A (en) * 1981-08-31 1983-03-05 Toshiba Corp Laminated semiconductor integrated circuit device
JPH0330301B2 (en) * 1981-08-31 1991-04-26
JPS5853821A (en) * 1981-09-25 1983-03-30 Toshiba Corp Preparation of laminated semiconductor device
JPS5856362A (en) * 1981-09-29 1983-04-04 Fujitsu Ltd Manufacturing method of semiconductor device
JPS6342418B2 (en) * 1981-09-29 1988-08-23 Fujitsu Ltd
JPS5893225A (en) * 1981-11-30 1983-06-02 Toshiba Corp Preparation of semiconductor thin film structure
JPS59182570A (en) * 1983-03-31 1984-10-17 Fujitsu Ltd semiconductor equipment
JPS60189217A (en) * 1984-03-09 1985-09-26 Agency Of Ind Science & Technol Seed structure for multilayer SOI
JPH0351086B2 (en) * 1984-03-09 1991-08-05 Kogyo Gijutsuin

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