JPS5837953A - Laminated semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To make small the delay of signal propagation by improving high integration density and short-cutting wiring length through the such element arrangement of field effect transistors of the same conductive channel that they are stacked vertically. CONSTITUTION:N channel MOSFET's, T1, T2, T3 are vertically connected at both the source and drain sides with the wiring layers 1, 2, 3 and 4. The power source line VSS is extended from the source side of the upper most layer III. P channel MOSFET's, T1', T2', T3' are connected vertically at the source of the lowest layerIand the source of the intermediate layer II, and with the drain of the intermediate layer II and the source of the upper most layer III respectively by the wiring layers 5 and 6. From the drain side of the upper most layer III, the power source line VDD is extended. In both N channel and P channel sides, the same conductive layers are stacked vertically resulting in the overlapping areas. The N channel side and P channel side are connected at the lowest layerIwith the wiring layer 7.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a stacked semiconductor integrated circuit device comprising a plurality of semiconductor layers in which elements including field effect transistors (FITs) are stacked with an insulating layer in between. Two matters.

The most prominent of the circuits that include N-channel and P-channel devices are complementary deaf circuits. Figure 1 is an example of 3
The human powered CM08NOi1 circuit is shown. 6 MOs 8
F Elte"1 e T* * T1 and 'I'
, ', TI', T,' are three input signals v1
1 v,, ■. It is opened and closed by ”meτ,,T,
are N-channel mTl・, te, ●, te. 1 is a P channel, so when ``1 * Tt * Tj is open, 'r
,','r,','r,' is closed, T,','r,I
, 'r,'' is open}!Tt-Tl*Tm is closed, and no DC current flows from VDD to Vll except at the moment of state transition.In other words, power consumption is extremely low, and in the future, L8I The larger the scale, the more important it becomes.
endpage:1 This is a circuit system that is becoming popular.

Conventionally, in order to assemble such a circuit, elements were arranged in a plane on the surface of a semiconductor such as 8M.

Figure 2 is an example of this, and is a layout diagram of the three-man powered CM08 NOR circuit shown in Figure 1 on the 81 crystal surface.
Le MO8FIT' JR child 4 F? Y*ru MO
All of the 8 FIfT elements are arranged on the same plane, so a special method called PWEL is used to separate the two types of elements. That is, a certain limited Pfi region is created on the Nll 81 crystal and is called a Pquel. N-channel MO8Fl'l'-T1~〒. is created in the P-well, and the P-channel MO8IPl'r. 'r1
'~T. 1 is made from the original N@8 top surface ζ. The reverse separation method is also possible; it is also possible to create an N-well on the surface of the P-type 81, an R-channel element inside the N-well, and an N-channel element outside the N-well. Such conventional integrated circuits have the following drawbacks.

First, it consumes a large area of the 81 surface.
Second, since a large number of input lines are placed on the same plane, long wiring is required between the input lines and the output section of the multi-stage circuit. In other words, if there is one input, it is possible to keep the previous circuit and the main circuit in close contact, but if there are multiple inputs,
There are also multiple circuits in the previous stage, and naturally they cannot be placed closely together. Inevitably, the wiring becomes long and the single-port GI
! This not only consumes a large amount of surface area, but also causes delays in signal propagation.

Although the CM08 circuit has been explained here as an example, the situation is the same in the case of a circuit composed only of N-channel FBTs or only P-channel Fl〒. The present invention aims at high density by laminating a plurality of semiconductor layers in which elements including Fl are integrated with an insulating layer in between, and is laminated under L. By setting the arrangement of Fil'r in a predetermined relationship, the wiring length can be shortened and the delay in signal propagation can be reduced, thereby providing a stable semiconductor integrated circuit device that can achieve high performance.

That is, in the present invention. The basic method is to construct a three-dimensional circuit by stacking semiconductor layers one above the other with insulating layers in between. Although this basic configuration is already a conventional concept, the feature of the present invention is that N-channel FIIT is N-channel FB? P-channel TNT and P-channel FET are lower ζ=
The purpose is to stack them so that they overlap. In this case, furthermore, the Flte which overlaps under L is the source, drain region and source, P drain region, ? It is preferable to set the element arrangement so that the r. This provides the advantage that the source or drain region, or both, can be directly connected under one layer.

The present invention provides the following advantages.

First, the area consumed on the substrate surface is significantly reduced, making it possible to create integrated circuits with high density.

Second, since the punching of the upper and lower semiconductor layers is performed in the same type of layer, a single crystal layer of JLL quality can be obtained with fewer crystal mismatches, and a device with high performance can be formed.

Thirdly, when forming one layer using a part of the lower layer as a seed crystal, the single crystal region to be controlled by the seed crystal is relatively narrow, and single crystallization can be achieved without difficulty, so the yield as L8I is also improved. It gets expensive.

Fourth, when constructing a multi-input NOR circuit, the inputs can be provided on different layers, making wiring with the preceding circuit block easy. By shortening the wiring length, signal propagation delay can be reduced, the area can be reduced, and the operating speed of the circuit can be increased.

As shown in Figure 5, output lines and power lines can also be installed on the desired layer.

Sixth, for example, when configuring a memory array I:
According to the present invention, each memory cell can be stacked vertically and the bit lines can be passed vertically, so a large number of outputs can be taken out. This point will be extremely useful for future computers that will be required to read a large number of memory contents at once.

endpage:2 Examples of the present invention will be described below.

(1) CM08 NOR circuit Figure 3 shows the three-man power CMO8 shown in Figure 1 based on the present invention.
This figure shows a schematic configuration of an example of a NOR circuit. The insulating layer is omitted for clarity. The semiconductor layer has a stacked structure of three layers 1 to 2, and the three layers on the left, FIT-TteTt*Ts, are N-channel MO8FBIT. These three FITs are connected vertically on both the source side (facing side) and drain side (front side) by wiring layers 1, 2, and 1.4, and the Vms power supply line is taken out from the source side of the top layer. There is. FFtT-71' of the three layers on the right, Tl@e Tl@ is P channel M
O8 Fli-cho, the bottom layer I is the source in front, and the middle layer ■
The source is on the opposite side, and the source is on the front side of the top layer. It is connected to 1 below.

A VDD conductor line is taken out from the drain side of the first layer ■. A feature is that layers of the same conductivity type are stacked one above the other on both the N-channel side and the P-channel side. N? With Yanel side! The channel side is connected by the bottom layer ■. That is, the N-channel MO8Fi'r of the bottom layer I
T, drain and P-channel MO8FET -. T
, ' are connected by the wiring layer r.

The inputs V1, v,,v, are distributed to each layer C; and are respectively %TI and T,′,D, and TI′*Tl and T,′(Dr-
} is connected. The output part ve is the middle class summer N channel MO8FIT-〒! However, it can be taken out from the first layer I or the bottom layer ■ as necessary. Also, the v1 line is the first layer I
It is also possible to place it in the middle layer ■ or the bottom layer I instead. According to this embodiment, when using the same design criteria as the conventional example C2hipe in FIG. 2, the area occupied by the 8-sho surface is 1/1! It decreases to below. This effect is even greater when the number of inputs is much larger, and based on this, the wiring can be shortened, and the signal transmission time is reduced in proportion to the square root of the area, achieving higher speeds. FIG. 4 shows a part of the sectional structure of the above embodiment. N-channel MO8FITs are stacked with the source, drain, and dirt aligned. Insulation 8 [8 is sio, for example. The sources and drains are each connected to the ground through wiring layers 1 to 4, and these parts are used as seed crystals to sequentially form the FIT of each layer! An 8i single crystal layer is formed. Since a layer of the same conductivity type as the seed portion is first grown, it has the advantage that it is easy to grow and it is easy to obtain crystals with high crystal quality. Moreover, since the area to be controlled by one Φ seed crystal is extremely narrow, single crystallization is easy, and IC
The yield is also significantly improved. However, since the channel section under the dart is slightly away from the seeds, it is easy to control the threshold voltage.

It is also possible to easily construct an N▲ND circuit in the same manner as in the above embodiment.

(2) Address decoder circuit FIG. S is a schematic diagram of an embodiment of an address decoder circuit operated by four people based on the present invention. The circuit has a laminated structure of 8 semiconductor layers.
OR. , ... are NO1 circuits powered by four people, for example, when configured with CMO8, @3 in Example (1)
The structure ζ is further stacked in the figure. However, in the case of this embodiment, FI is installed in selected four layers among the eight layers.
T is formed, and the other layers are vacant.

AIs▲@, 1B, ▲4 are address inputs, ▲,, ▲,
, ▲1, Person 4 is the opposite. These eight are distributed to each of the eight layers, and are connected to ff-} of the corresponding layer of NOR, , NOR, . . . , excluding vacant positions. For example, NOR is the address (▲1 , ▲,, ▲., ▲
4) Outputs 1 when (0, 0, 0.0).
ndpage:3 If you decide on a sea urchin, NOR is ▲, . ▲，，▲Hatake ，
There is a Fl block on the 4th floor corresponding to ▲6, and the corresponding positions on the other 4 floors are vacant. Next, if we decide that Non, outputs 1 when the address is (0, 0, 0, 1), then NOR, is A1, ▲@, k@, A
There is a FIT in the 4th layer corresponding to the number, and the corresponding positions in other layers are vacant. Similarly, NOi
The structure of l, , NOR4, --... is determined.

As shown in FIG. 3 of the previous embodiment (1), each NO1 circuit has a stack of dry APIITs on the left side, so its source and P-rain are connected vertically. Therefore, output can be extracted from any layer. In Figure 5, the front side is the drain side of the dry ΔFET,
The case where outputs 0,,0,,... are extracted from all layers is shown. This embodiment ζ: Therefore, the board area is reduced and the signal propagation speed is increased. Effects such as improved circuit characteristics and improved yields can be obtained through JL-quality crystal growth.

(3) CMOS static memory circuit FIG. 6 is a schematic diagram of an embodiment in which a CMOS 8 static memory cell is constructed based on the present invention.

(m, n) (m=1.2,...; 11-
1. If a memory cell is represented by (2,...), then (1
, n) , (2, m), ... are stacked vertically, Wm (m-depth 1, 2, ...) is the warp line, W, is the top layer, and W, is the next layer. The wiring is done in layers, etc. Bn, B! l (aml, 2, "・) is the Vt line, and the memory cells (1, m), (
2, n)... are connected to the input/output section. Vl)D is a High side electric wire, and VII is a LlIW side power supply line. A feature is that VDD and Vss are also connected to memory cells stacked one above the other.

Inside the mesori cell, there is one each on both ends of CMO & Frigg Frog.
transfer r-}MO8FIT'rise〒14
This is a so-called static memory cell. 〒
11* “He 'lU* T14 is N?+$leM08
Fl〒,τ,,',〒11' is pfJr channel MO 8
FB〒. In FIG. 6, each pm'r is shown by a symbol, but structurally, Flte represented by the same era code are arranged so as to overlap vertically. For example, te,1
In the cell (1,!I), in the cell (2, Otori), and in the cell (m, Otori), they all overlap in a skin-like manner, and the drain region overlaps the drain region. What's wrong with each other, what's the source area with the source area? -} area exactly overlaps the ff-} area. Moreover, which FB
The characteristic of the T is that either the teeth or the drain are tied at the top and bottom at one end.

According to this embodiment, since the lower layer is connected by the same conductivity type layer, it is easy to create a single crystal layer of the soil layer using the connection part with the lower layer as a seed crystal. Moreover, each r
Since one end of NTE is always located at 1 of the lower seed crystal, the single crystallization rate is good and the cathar mobility is high. In addition, the bit line can be made extremely short, and the signal propagation delay due to wiring can be minimized, making it possible to use access lines as a memory.
can be made shorter. Furthermore, by expanding this structure laterally and arranging many memory cells, it is possible to extract many pit lines. This point is important for applications that require reading a large number of memory contents at once, such as associative memory,
It is extremely useful for image information processing.

In the above embodiments, the CM08 circuit was used, but the N-channel MO8% P-channel circuit. The present invention can be similarly applied to MO8 circuits. Also FIT}tMO8FIIT
}? Karitep < Mlii8Fii Dingtemo can be applied. Furthermore, in the embodiment of the first generation memory circuit, a static RAM is shown, but in the same way, a dynamic RAM JpROM
can also be configured in the same way, and similar effects can be achieved.

endpage:4

[Brief explanation of drawings]

Fig. 1 shows the CM08 NOR circuit, Fig. 2 shows the CM08 NOR circuit integrated on an 8N substrate, and Fig. 3 shows the CM08 NOR circuit.
A diagram showing a schematic configuration of an embodiment of the present invention in which R circuits are three-dimensionally integrated, the fourth factor is a diagram showing a cross-sectional structure of a part of the circuit, and FIG. 5 is a diagram in which the present invention is applied to an address decoder. FIG. 6 is a diagram showing a schematic configuration of an embodiment in which the present invention is applied to a CMO8 static memory. T1 s ”le Tm...N channel MO8
Fl! tT,〒. ', Tl', T, I...P channel MO8FET%I, 1.1... Semiconductor layer, 1-1
...Wiring layer, 8...Insulating layer, T11#"lt*〒l
aw〒、、・・・N? Yanel MO8PI! tT. ? 11
1, dingu'""Pf'r*#MO8FET, (1*
a) * (2 en) e...(m,!
l)... Memotsu cell. Applicant's representative Patent attorney Takehiko Suzueendpage:5

Claims (3)

[Claims] (1) In a semiconductor integrated circuit device that is constructed by laminating multiple semiconductor layers with integrated insulating layers in between, in which elements including field effect transistors are formed, field effect transistors with the same conductive channel are stacked vertically. A stacked semiconductor integrated circuit device characterized in that an element arrangement is set in the following. (2) The stacked semiconductor integrated circuit device according to claim 1, wherein the vertically overlapping field effect transistors are arranged such that their respective source, drain regions, and r-F regions overlap with each other. (3) The field effect transistors that overlap under L have their respective sources. The laminated semiconductor integrated circuit device according to claim 1, wherein the P-rain region and the Y-node region are arranged so as to overlap each other, and at least one of the source and drain regions is connected vertically. .