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JPS5659354A - Pseudo fault test system - Google Patents

Pseudo fault test system

Info

Publication number
JPS5659354A
JPS5659354A JP13485679A JP13485679A JPS5659354A JP S5659354 A JPS5659354 A JP S5659354A JP 13485679 A JP13485679 A JP 13485679A JP 13485679 A JP13485679 A JP 13485679A JP S5659354 A JPS5659354 A JP S5659354A
Authority
JP
Japan
Prior art keywords
pseudo fault
processor
pseudo
setting condition
instruction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13485679A
Other languages
Japanese (ja)
Inventor
Yoshihiro Kudo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP13485679A priority Critical patent/JPS5659354A/en
Publication of JPS5659354A publication Critical patent/JPS5659354A/en
Pending legal-status Critical Current

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  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

PURPOSE: To check to ensure that the function of the central processor is normal, by providing a memory part for storing plural group information consisting of the pseudo fault setting condition and the pseudo fault information, and automatically inserting a pseudo fault from other processor.
CONSTITUTION: When a maintenance exclusive instruction is stored and decoded in the instruction register 11 of the central processor 10, an interruption signal is provided to other processor 20 from the line 16, and other processor stores a data part of the maintenance exclusive instruction from the processor 10. In the memory part 25 of the processor 20 are stored plural groups consisting of the pseudo fault setting condition and the pseudo fault information in advance, one of them is selected by a data which has been read, the sequence which has received the test instruction is made to proceed by the pseudo fault setting condition, a pseudo fault signal is set through the signal line 22 in accordance with the pseudo fault information, a clock is started through the clock start signal line 23, and it is confirmed that the machine check processing function of the processor 10 is normal.
COPYRIGHT: (C)1981,JPO&Japio
JP13485679A 1979-10-18 1979-10-18 Pseudo fault test system Pending JPS5659354A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13485679A JPS5659354A (en) 1979-10-18 1979-10-18 Pseudo fault test system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13485679A JPS5659354A (en) 1979-10-18 1979-10-18 Pseudo fault test system

Publications (1)

Publication Number Publication Date
JPS5659354A true JPS5659354A (en) 1981-05-22

Family

ID=15138060

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13485679A Pending JPS5659354A (en) 1979-10-18 1979-10-18 Pseudo fault test system

Country Status (1)

Country Link
JP (1) JPS5659354A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6158051A (en) * 1984-08-28 1986-03-25 Nec Corp False trouble generating system
JPH02128237A (en) * 1988-11-08 1990-05-16 Nec Corp Information processor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6158051A (en) * 1984-08-28 1986-03-25 Nec Corp False trouble generating system
JPH02128237A (en) * 1988-11-08 1990-05-16 Nec Corp Information processor

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