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JPS5634197A - Memory unit - Google Patents

Memory unit

Info

Publication number
JPS5634197A
JPS5634197A JP10879679A JP10879679A JPS5634197A JP S5634197 A JPS5634197 A JP S5634197A JP 10879679 A JP10879679 A JP 10879679A JP 10879679 A JP10879679 A JP 10879679A JP S5634197 A JPS5634197 A JP S5634197A
Authority
JP
Japan
Prior art keywords
block
memory
address
unit
sets
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10879679A
Other languages
Japanese (ja)
Other versions
JPS5935120B2 (en
Inventor
Kazumitsu Matsuzawa
Tsutomu Ishikawa
Noboru Onishi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP54108796A priority Critical patent/JPS5935120B2/en
Publication of JPS5634197A publication Critical patent/JPS5634197A/en
Publication of JPS5935120B2 publication Critical patent/JPS5935120B2/en
Expired legal-status Critical Current

Links

Landscapes

  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

PURPOSE: To reduce the unit of change-over than the memory unit, without causing section loss, by sectioning the memory unit into a plurality of blocks and performing accessing to normal block at the change-over circuit corresponding to each block.
CONSTITUTION: The memory unit 1 consists of n sets of memory units 2, and each unit 2 consists of the memory section 4, 2X×2Y sets of change-over circuits 3, and conversion circuit 28. The memory section 4 is logically sectioned into 2X×2Y sets of memory blocks designated with the block address 29. The circuit 3 corresponds to each block by one to one, and the flag 11 displays the deficiency of block. The memory section 4 selects and drives the cell with X block address 25, Y block address 26, address 30 in X block from the address information 22 accessed, and address 31 in Y block, and the data signal 9 is received and transmitted on the bus 10.
COPYRIGHT: (C)1981,JPO&Japio
JP54108796A 1979-08-27 1979-08-27 memory device Expired JPS5935120B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP54108796A JPS5935120B2 (en) 1979-08-27 1979-08-27 memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP54108796A JPS5935120B2 (en) 1979-08-27 1979-08-27 memory device

Publications (2)

Publication Number Publication Date
JPS5634197A true JPS5634197A (en) 1981-04-06
JPS5935120B2 JPS5935120B2 (en) 1984-08-27

Family

ID=14493696

Family Applications (1)

Application Number Title Priority Date Filing Date
JP54108796A Expired JPS5935120B2 (en) 1979-08-27 1979-08-27 memory device

Country Status (1)

Country Link
JP (1) JPS5935120B2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6336420Y2 (en) * 1984-09-06 1988-09-27
JPH018424Y2 (en) * 1984-09-06 1989-03-07
JPS61262254A (en) * 1985-05-11 1986-11-20 Toyota Motor Corp Power distributing apparatus for car

Also Published As

Publication number Publication date
JPS5935120B2 (en) 1984-08-27

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