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JPS5633821A - Photoannealing method for semiconductor layer - Google Patents

Photoannealing method for semiconductor layer

Info

Publication number
JPS5633821A
JPS5633821A JP10912879A JP10912879A JPS5633821A JP S5633821 A JPS5633821 A JP S5633821A JP 10912879 A JP10912879 A JP 10912879A JP 10912879 A JP10912879 A JP 10912879A JP S5633821 A JPS5633821 A JP S5633821A
Authority
JP
Japan
Prior art keywords
layer
defectless
silicon
semiconductor layer
photoannealing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10912879A
Other languages
Japanese (ja)
Inventor
Seiichi Iwamatsu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CHIYOU LSI GIJUTSU KENKYU KUMIAI
CHO LSI GIJUTSU KENKYU KUMIAI
Original Assignee
CHIYOU LSI GIJUTSU KENKYU KUMIAI
CHO LSI GIJUTSU KENKYU KUMIAI
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by CHIYOU LSI GIJUTSU KENKYU KUMIAI, CHO LSI GIJUTSU KENKYU KUMIAI filed Critical CHIYOU LSI GIJUTSU KENKYU KUMIAI
Priority to JP10912879A priority Critical patent/JPS5633821A/en
Publication of JPS5633821A publication Critical patent/JPS5633821A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Optics & Photonics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Electromagnetism (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

PURPOSE:To make possible to crystallize a semiconductor layer keeping the state of the entire layer defectless by applying photoannealing treatment two times or more in the thickness direction of the semiconductor layer. CONSTITUTION:On the surface of a sapphire substrate 1, an epitaxial silicon layer 2 is formed. In such construction of an SOS, many crystal defects exist on the sapphire silicon boundary while less crystal defects exist on the silicon surface, therefore an amorphous layer 3 is formed by implanting ions of, for example, Ar to the boundary, and by irradiating laser beams to the layer to anneal it, a defectless monocrystalline layer 4 is formed. Next, Ar ions are implanted to the surface of the silicon layer, and by annealing with laser beams, the surface is made defectless and converted into a defectless monocrystalline layer 6. By so doing, the entire silicon layer can be made completely defectless.
JP10912879A 1979-08-29 1979-08-29 Photoannealing method for semiconductor layer Pending JPS5633821A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10912879A JPS5633821A (en) 1979-08-29 1979-08-29 Photoannealing method for semiconductor layer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10912879A JPS5633821A (en) 1979-08-29 1979-08-29 Photoannealing method for semiconductor layer

Publications (1)

Publication Number Publication Date
JPS5633821A true JPS5633821A (en) 1981-04-04

Family

ID=14502277

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10912879A Pending JPS5633821A (en) 1979-08-29 1979-08-29 Photoannealing method for semiconductor layer

Country Status (1)

Country Link
JP (1) JPS5633821A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58135630A (en) * 1982-02-08 1983-08-12 Fujitsu Ltd Annealing method for semiconductor layer
US4509990A (en) * 1982-11-15 1985-04-09 Hughes Aircraft Company Solid phase epitaxy and regrowth process with controlled defect density profiling for heteroepitaxial semiconductor on insulator composite substrates
US5021119A (en) * 1987-11-13 1991-06-04 Kopin Corporation Zone-melting recrystallization process
US5298434A (en) * 1992-02-07 1994-03-29 Harris Corporation Selective recrystallization to reduce P-channel transistor leakage in silicon-on-sapphire CMOS radiation hardened integrated circuits
US5453153A (en) * 1987-11-13 1995-09-26 Kopin Corporation Zone-melting recrystallization process
US6383899B1 (en) * 1996-04-05 2002-05-07 Sharp Laboratories Of America, Inc. Method of forming polycrystalline semiconductor film from amorphous deposit by modulating crystallization with a combination of pre-annealing and ion implantation
KR100972605B1 (en) * 2008-03-19 2010-07-28 동국대학교 산학협력단 Method for manufacturing silicon laminated sapphire thin film and thereby manufactured silicon laminated sapphire thin film

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58135630A (en) * 1982-02-08 1983-08-12 Fujitsu Ltd Annealing method for semiconductor layer
US4509990A (en) * 1982-11-15 1985-04-09 Hughes Aircraft Company Solid phase epitaxy and regrowth process with controlled defect density profiling for heteroepitaxial semiconductor on insulator composite substrates
US5021119A (en) * 1987-11-13 1991-06-04 Kopin Corporation Zone-melting recrystallization process
US5453153A (en) * 1987-11-13 1995-09-26 Kopin Corporation Zone-melting recrystallization process
US5298434A (en) * 1992-02-07 1994-03-29 Harris Corporation Selective recrystallization to reduce P-channel transistor leakage in silicon-on-sapphire CMOS radiation hardened integrated circuits
US6383899B1 (en) * 1996-04-05 2002-05-07 Sharp Laboratories Of America, Inc. Method of forming polycrystalline semiconductor film from amorphous deposit by modulating crystallization with a combination of pre-annealing and ion implantation
KR100972605B1 (en) * 2008-03-19 2010-07-28 동국대학교 산학협력단 Method for manufacturing silicon laminated sapphire thin film and thereby manufactured silicon laminated sapphire thin film

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