[go: up one dir, main page]

JPS56166527A - Time division time slot assigning system - Google Patents

Time division time slot assigning system

Info

Publication number
JPS56166527A
JPS56166527A JP6841680A JP6841680A JPS56166527A JP S56166527 A JPS56166527 A JP S56166527A JP 6841680 A JP6841680 A JP 6841680A JP 6841680 A JP6841680 A JP 6841680A JP S56166527 A JPS56166527 A JP S56166527A
Authority
JP
Japan
Prior art keywords
line
signal
address
devices
time slot
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6841680A
Other languages
Japanese (ja)
Inventor
Akira Kawasaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP6841680A priority Critical patent/JPS56166527A/en
Publication of JPS56166527A publication Critical patent/JPS56166527A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)
  • Small-Scale Networks (AREA)

Abstract

PURPOSE:To obtain a time division TS assigning system with high reliability with one address line, by transferring an address signal giving a time slot TS serially with selected sequences. CONSTITUTION:Data transferring devices A, B, and C are connected to one address line AD, timing line TI and data line DA, respectively. A clock signal to the TI line and a binary sequence train signal to the AD line are produced from a signal generating circuit X, and the binary sequence is outputted in synchronizing with the clock signal. The AD line signal is fetched in a shift register SR by the devices A-C in synchronizing with the clock. The output of the SR is compared with an address code to be given, and when they coincide, the TS for data transfer is given to the devices. Further, by specifying the sequence of the AD line by a system, since the error in the AD line signal can be corrected from the bit trains before and after, the system reliability can be increasd.
JP6841680A 1980-05-24 1980-05-24 Time division time slot assigning system Pending JPS56166527A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6841680A JPS56166527A (en) 1980-05-24 1980-05-24 Time division time slot assigning system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6841680A JPS56166527A (en) 1980-05-24 1980-05-24 Time division time slot assigning system

Publications (1)

Publication Number Publication Date
JPS56166527A true JPS56166527A (en) 1981-12-21

Family

ID=13373049

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6841680A Pending JPS56166527A (en) 1980-05-24 1980-05-24 Time division time slot assigning system

Country Status (1)

Country Link
JP (1) JPS56166527A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0344356U (en) * 1989-09-01 1991-04-24

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0344356U (en) * 1989-09-01 1991-04-24

Similar Documents

Publication Publication Date Title
JPS5639694A (en) Method and device for synchrnonizing timing in transmission of digital information signal
GB1410921A (en) Data terminals
EP0311448A2 (en) Digital multiplexer
GB1507093A (en) Arrangements for correcting slip errors in pulse-code transmission systems
JPS56166527A (en) Time division time slot assigning system
GB1528273A (en) Methods of and apparatus for the encoded transmission of information
JPS5696552A (en) Erastic storage
SU1396139A1 (en) Adder
JPS56111350A (en) Error control system
SU1259506A1 (en) Start-stop reception device
SU1099321A1 (en) Device for transmitting and receiving digital information
SU1615769A1 (en) Device for receiving data
SU1509897A1 (en) Signature analyzer
SU536609A1 (en) Device for dividing pulse frequency with discrete control
SU1172047A1 (en) Device for transmission and reception of digital signals
SU1554143A1 (en) Binary-coded decimal code-to-binary code converter
JPS6276876A (en) Synchronization detecting device
SU906014A1 (en) Device for phase starting of receiver
SU1124310A1 (en) Device for calculating modulo convolution
SU639003A1 (en) Information receiving arrangement
SU873445A1 (en) Cycle-wise synchronization device
FR2307405A1 (en) Time or clock pulse control system - has terminal or subscriber station(s) connected by microwave transmission line
SU1598191A1 (en) Device for receiving bi-pulse signals
JPS5739639A (en) Delay type phase correction system
SU1401629A1 (en) Device for asynchronous matching of synchronous binary signals