JPS5739639A - Delay type phase correction system - Google Patents
Delay type phase correction systemInfo
- Publication number
- JPS5739639A JPS5739639A JP55115523A JP11552380A JPS5739639A JP S5739639 A JPS5739639 A JP S5739639A JP 55115523 A JP55115523 A JP 55115523A JP 11552380 A JP11552380 A JP 11552380A JP S5739639 A JPS5739639 A JP S5739639A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- phase correction
- bit
- frame
- delay circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Time-Division Multiplex Systems (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
PURPOSE:To demodulate a high-speed digital signal and to synchronize it to a clock in the device, by connecting two stages of phase correction circuits by delay circuit serially. CONSTITUTION:The output of a cable receiver 20 demodulating a digital signal on a time division digital transmission line is made for phase correction with a bit phase correction circuit 30 by a bit delay circuit 31 and a frame phase correction circuit 40 by a frame delay circuit 41. That is, in the cable receiver 20, a digital signal is separated into a clock CLK in synchronizing with the data, frame pulse and input information and they are inputted to the circuit 30. The output of the bit delay circuit 31 sequentially delaying the data and the frame pulse, the clock CLK, and the output of a bit phase comparison circuit 32 in phase comparison with a clock 50 in the device, are applied to a bit synchronizing circuit 33 to take bit synchronism. Similarly, the frame phase correction circuit 40 takes frame synchonism.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55115523A JPS5739639A (en) | 1980-08-22 | 1980-08-22 | Delay type phase correction system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55115523A JPS5739639A (en) | 1980-08-22 | 1980-08-22 | Delay type phase correction system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5739639A true JPS5739639A (en) | 1982-03-04 |
Family
ID=14664629
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP55115523A Pending JPS5739639A (en) | 1980-08-22 | 1980-08-22 | Delay type phase correction system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5739639A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6223647A (en) * | 1985-02-13 | 1987-01-31 | ボルト ベラネク アンド ニユ−マン インク | Digital phase adjuster |
| US4860867A (en) * | 1986-07-14 | 1989-08-29 | Sanden Corporation | Electromagnetic clutch |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5061970A (en) * | 1973-09-29 | 1975-05-27 |
-
1980
- 1980-08-22 JP JP55115523A patent/JPS5739639A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5061970A (en) * | 1973-09-29 | 1975-05-27 |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6223647A (en) * | 1985-02-13 | 1987-01-31 | ボルト ベラネク アンド ニユ−マン インク | Digital phase adjuster |
| US4860867A (en) * | 1986-07-14 | 1989-08-29 | Sanden Corporation | Electromagnetic clutch |
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