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JPS56155540A - Mounting structure of semiconductor device - Google Patents

Mounting structure of semiconductor device

Info

Publication number
JPS56155540A
JPS56155540A JP5979480A JP5979480A JPS56155540A JP S56155540 A JPS56155540 A JP S56155540A JP 5979480 A JP5979480 A JP 5979480A JP 5979480 A JP5979480 A JP 5979480A JP S56155540 A JPS56155540 A JP S56155540A
Authority
JP
Japan
Prior art keywords
protruding electrode
center
tape
hole
pouring hole
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5979480A
Other languages
Japanese (ja)
Inventor
Kazuo Inoue
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Citizen Watch Co Ltd
Original Assignee
Citizen Watch Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Citizen Watch Co Ltd filed Critical Citizen Watch Co Ltd
Priority to JP5979480A priority Critical patent/JPS56155540A/en
Publication of JPS56155540A publication Critical patent/JPS56155540A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/79—Apparatus for Tape Automated Bonding [TAB]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/86—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using tape automated bonding [TAB]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To obtain the small-sized and thin-typed semiconductor device by a method wherein a hole which is wider than the protruding electrode at the element mounting section of an elastic tape is provided at the point corresponding to the protruding electrode and also the pouring hole of a molding material is provided at the location corresponding to the center of the element. CONSTITUTION:An inner frame 2d is formed by providing the gap 2e, which is wider than a pilot hole 2a and the protruding electrode 4a of the element 4 at the position where they are facing each other, and the pouring hole 2c of the molding material 6 at the position facing the center of the element 4. Then, a long-sized copper foil is adhered to the center of the tape 2 and the prescribed circuit pattern is formed by performing an etching. The finger 3b of the pattern is formed into bridge type between the tape 2 and the frame 2d. An Sn plating is performed on the finger 3b and it is joined together using a gold and tin eutectic with the protruding electrode 4a, and a circuit substrate 1 and the element 4 are connected. Then, the mold material 6 is poured from the pouring hole 2c. Through this constitution, the device can be miniaturized and thin typed, and the process of manufacture and the number of parts needed can be reduced as well.
JP5979480A 1980-05-06 1980-05-06 Mounting structure of semiconductor device Pending JPS56155540A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5979480A JPS56155540A (en) 1980-05-06 1980-05-06 Mounting structure of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5979480A JPS56155540A (en) 1980-05-06 1980-05-06 Mounting structure of semiconductor device

Publications (1)

Publication Number Publication Date
JPS56155540A true JPS56155540A (en) 1981-12-01

Family

ID=13123533

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5979480A Pending JPS56155540A (en) 1980-05-06 1980-05-06 Mounting structure of semiconductor device

Country Status (1)

Country Link
JP (1) JPS56155540A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5681777A (en) * 1992-06-04 1997-10-28 Lsi Logic Corporation Process for manufacturing a multi-layer tab tape semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5681777A (en) * 1992-06-04 1997-10-28 Lsi Logic Corporation Process for manufacturing a multi-layer tab tape semiconductor device

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