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JPS5710951A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5710951A
JPS5710951A JP8679280A JP8679280A JPS5710951A JP S5710951 A JPS5710951 A JP S5710951A JP 8679280 A JP8679280 A JP 8679280A JP 8679280 A JP8679280 A JP 8679280A JP S5710951 A JPS5710951 A JP S5710951A
Authority
JP
Japan
Prior art keywords
resin
semiconductor element
ceramic substrate
ceramic
warp
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8679280A
Other languages
Japanese (ja)
Inventor
Hideo Taniguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Toyo Electronics Industry Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd, Toyo Electronics Industry Corp filed Critical Rohm Co Ltd
Priority to JP8679280A priority Critical patent/JPS5710951A/en
Publication of JPS5710951A publication Critical patent/JPS5710951A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE:To reduce the thermal stress between resin and ceramic and prevent the warp of a ceramic substrate and the separation of the resin, by a method wherein a semiconductor element secured to the ceramic substrate is sealed with resin, and a ceramic piece is attached to the resin. CONSTITUTION:On a ceramic substrate 1, a conducting terminal part 2 and a semiconductor element mounting part 3 are formed, and a semiconductor element 4 is mounted. Said semiconductor element 4 is connected to the conducting terminal part 2 through thin metal wires 5. This is coated with a resin layer 6, and before the resin 6 has hardened, a ceramic piece 7 is mounted and secured thereto. Thereby, the thermal stress generated in the thermal contraction of the resin is reduced. Accordingly, there is no possibility of the warp of the ceramic substrate and the separation of the resin. Moreover, the stress to the thin metal wires 5 decreases. Therefore, disconnection and connection failures decreases.
JP8679280A 1980-06-25 1980-06-25 Semiconductor device Pending JPS5710951A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8679280A JPS5710951A (en) 1980-06-25 1980-06-25 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8679280A JPS5710951A (en) 1980-06-25 1980-06-25 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5710951A true JPS5710951A (en) 1982-01-20

Family

ID=13896619

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8679280A Pending JPS5710951A (en) 1980-06-25 1980-06-25 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5710951A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002097880A2 (en) * 2001-05-25 2002-12-05 eupec Europäische Gesellschaft für Leistungshalbleiter mbH & Co. KG Power semiconductor module and method for the production of a power semiconductor module
US6638573B1 (en) 1999-07-14 2003-10-28 Osaka Municipal Government Spectacles frame surface treatment method
JP2014107547A (en) * 2012-11-29 2014-06-09 Samsung Electro-Mechanics Co Ltd Electronic component package
JP2017204494A (en) * 2016-05-09 2017-11-16 オリンパス株式会社 Electronic substrate for medical equipment

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4828300U (en) * 1971-08-06 1973-04-06

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4828300U (en) * 1971-08-06 1973-04-06

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6638573B1 (en) 1999-07-14 2003-10-28 Osaka Municipal Government Spectacles frame surface treatment method
WO2002097880A2 (en) * 2001-05-25 2002-12-05 eupec Europäische Gesellschaft für Leistungshalbleiter mbH & Co. KG Power semiconductor module and method for the production of a power semiconductor module
WO2002097880A3 (en) * 2001-05-25 2003-09-25 Eupec Gmbh & Co Kg Power semiconductor module and method for the production of a power semiconductor module
JP2014107547A (en) * 2012-11-29 2014-06-09 Samsung Electro-Mechanics Co Ltd Electronic component package
JP2017204494A (en) * 2016-05-09 2017-11-16 オリンパス株式会社 Electronic substrate for medical equipment

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