JPS56153423A - Interdevice communication system - Google Patents
Interdevice communication systemInfo
- Publication number
- JPS56153423A JPS56153423A JP5682680A JP5682680A JPS56153423A JP S56153423 A JPS56153423 A JP S56153423A JP 5682680 A JP5682680 A JP 5682680A JP 5682680 A JP5682680 A JP 5682680A JP S56153423 A JPS56153423 A JP S56153423A
- Authority
- JP
- Japan
- Prior art keywords
- devices
- signal
- transferred
- control
- channel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/10—Program control for peripheral devices
- G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
- G06F13/122—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
Abstract
PURPOSE:To make control information or instruction information transferable between a channel controller and channel devices by reading the values of the address register of the control memory of a subprocessor in a master processor and writing the values of the address register according to the states thereof. CONSTITUTION:A channel controller 3 and plural channel devices 4 are coupled by means of an interface bus 100, and the control information transmitted from the devices 4 to the device 3 and the instruction information transmitted from the device 3 to the devices 4 are transferred by way of the bus 100. As shown by dotted lines, the devices 4 and the device 3 are coupled respectively by means of microcommand control lines, so that the interruption signal 112 is transferred from the devices 4 to the other device and the address transmission instruction signal 105, the interruption reception signal 111, the execution restarting signal 121, and the address set signal 140 are transferred from the device 3 to the other devices via the control line.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5682680A JPS56153423A (en) | 1980-04-28 | 1980-04-28 | Interdevice communication system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5682680A JPS56153423A (en) | 1980-04-28 | 1980-04-28 | Interdevice communication system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS56153423A true JPS56153423A (en) | 1981-11-27 |
Family
ID=13038175
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5682680A Pending JPS56153423A (en) | 1980-04-28 | 1980-04-28 | Interdevice communication system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56153423A (en) |
-
1980
- 1980-04-28 JP JP5682680A patent/JPS56153423A/en active Pending
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