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JPS56146891A - Selective plating method - Google Patents

Selective plating method

Info

Publication number
JPS56146891A
JPS56146891A JP4975680A JP4975680A JPS56146891A JP S56146891 A JPS56146891 A JP S56146891A JP 4975680 A JP4975680 A JP 4975680A JP 4975680 A JP4975680 A JP 4975680A JP S56146891 A JPS56146891 A JP S56146891A
Authority
JP
Japan
Prior art keywords
marker
layer
pattern
case
resist
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4975680A
Other languages
Japanese (ja)
Other versions
JPS6024189B2 (en
Inventor
Akira Amano
Takayuki Konuma
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP55049756A priority Critical patent/JPS6024189B2/en
Publication of JPS56146891A publication Critical patent/JPS56146891A/en
Publication of JPS6024189B2 publication Critical patent/JPS6024189B2/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods

Landscapes

  • Electroplating Methods And Accessories (AREA)

Abstract

PURPOSE: To plate only on the required area of a semiconductor plate surface by making a photoresist layer thick and the line width of a marker finer, and melt- sticking the resist sandwiching the marker line part at the time of heat treatment.
CONSTITUTION: A photomask 23 is superposed on an Si substrate 21 having beforehand been coated with a photoresist layer 22 in such a manner that said marker pattern 24 aligns to the marker 25 visible through the resist layer 22 on the substrate 21, after which ultraviolet rays 26 are irradiated. The ultraviolet rays 26 are shut off by the electrode pattern 27 and marker pattern 24 provided to the mask 23 and expose the resist layer 22 of other parts, thereby making the same insoluble to solvents. In this case, the thickness of the regist layer 22 is made several times that in an ordinary case so that the line width of the pattern 24 is made fairly finer than that of an ordinary case. As a result of development, windows 28, 29 are produced in the resist layer 22, but if heat treatment is applied in succession for the purpose of solidification, the window 28 of the marker part is melt-stuck by the swelling of the layer 22 on both sides, and in the case of forming bump electrodes 30 by electroplating, the plating on the marker 25 is prevented.
COPYRIGHT: (C)1981,JPO&Japio
JP55049756A 1980-04-15 1980-04-15 Selective plating method Expired JPS6024189B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55049756A JPS6024189B2 (en) 1980-04-15 1980-04-15 Selective plating method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55049756A JPS6024189B2 (en) 1980-04-15 1980-04-15 Selective plating method

Publications (2)

Publication Number Publication Date
JPS56146891A true JPS56146891A (en) 1981-11-14
JPS6024189B2 JPS6024189B2 (en) 1985-06-11

Family

ID=12840025

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55049756A Expired JPS6024189B2 (en) 1980-04-15 1980-04-15 Selective plating method

Country Status (1)

Country Link
JP (1) JPS6024189B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6054456A (en) * 1983-09-05 1985-03-28 Oki Electric Ind Co Ltd Forming method of bump electrode

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6054456A (en) * 1983-09-05 1985-03-28 Oki Electric Ind Co Ltd Forming method of bump electrode

Also Published As

Publication number Publication date
JPS6024189B2 (en) 1985-06-11

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