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JPS56110167A - Redisposing method of computer main storage device - Google Patents

Redisposing method of computer main storage device

Info

Publication number
JPS56110167A
JPS56110167A JP1343780A JP1343780A JPS56110167A JP S56110167 A JPS56110167 A JP S56110167A JP 1343780 A JP1343780 A JP 1343780A JP 1343780 A JP1343780 A JP 1343780A JP S56110167 A JPS56110167 A JP S56110167A
Authority
JP
Japan
Prior art keywords
bank
selectors
selector
gates
arrangement
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1343780A
Other languages
Japanese (ja)
Inventor
Nobuo Nakagawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP1343780A priority Critical patent/JPS56110167A/en
Publication of JPS56110167A publication Critical patent/JPS56110167A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/18—Handling requests for interconnection or transfer for access to memory bus based on priority control

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)

Abstract

PURPOSE:To enable easy redisposition, disconnection and changing-over of storages by providing a bank selector and bank arrangement selectors through input-output ports for storage banks or storage increase units and enabling both selectors to be reset. CONSTITUTION:Input-output ports 7 are respectively connected to a CPU1, and a bank selector 8 is connected to one port 7 and bank arrangement selectors 12a, 12b are connected to the other ports 7. The selectors 8 and 12a, 12b are connected to the bank enable gates 13a, 13b of a bank connection switch 10. These gates 13a, 13b are connected respectively to storage banks 2a, 2b through bank enable lines 11, the arrangement of the banks 2a, 2b are set and the bank 2a or 2b to be used is set by the selector 8. The bank 2a or 2b for which the selectors 12a, 12b and the selector 8 coincide through the gates 13a, 13b is made usable, whereby the redisposition, disconnection and changing-over of storages are easily made.
JP1343780A 1980-02-06 1980-02-06 Redisposing method of computer main storage device Pending JPS56110167A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1343780A JPS56110167A (en) 1980-02-06 1980-02-06 Redisposing method of computer main storage device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1343780A JPS56110167A (en) 1980-02-06 1980-02-06 Redisposing method of computer main storage device

Publications (1)

Publication Number Publication Date
JPS56110167A true JPS56110167A (en) 1981-09-01

Family

ID=11833100

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1343780A Pending JPS56110167A (en) 1980-02-06 1980-02-06 Redisposing method of computer main storage device

Country Status (1)

Country Link
JP (1) JPS56110167A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58501972A (en) * 1981-11-17 1983-11-17 ヒュンダイ・エレクトロニクス・インダストリーズ・カンパニー・リミテッド memory mapping unit

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5057342A (en) * 1973-09-19 1975-05-19

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5057342A (en) * 1973-09-19 1975-05-19

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58501972A (en) * 1981-11-17 1983-11-17 ヒュンダイ・エレクトロニクス・インダストリーズ・カンパニー・リミテッド memory mapping unit

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