JPS5727363A - Vector data processor - Google Patents
Vector data processorInfo
- Publication number
- JPS5727363A JPS5727363A JP10153680A JP10153680A JPS5727363A JP S5727363 A JPS5727363 A JP S5727363A JP 10153680 A JP10153680 A JP 10153680A JP 10153680 A JP10153680 A JP 10153680A JP S5727363 A JPS5727363 A JP S5727363A
- Authority
- JP
- Japan
- Prior art keywords
- vector
- banks
- vector data
- data processor
- register
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
- G06F15/8053—Vector processors
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Theoretical Computer Science (AREA)
- Computing Systems (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Complex Calculations (AREA)
Abstract
PURPOSE:To facilitate control by preventing access requests from colliding with each other in a bank while employing multiplebank constitution for vector registers. CONSTITUTION:Vector registers are composed of banks B0-B7. Respective elements #0, #1-#8. of the vector registers VR0, VR1-VR8 are stored in the banks B0, B1-B8. Similarly, elements are assigned to the banks, and readout vector data are synchronized by a buffer register 5, thereby inputting the element #i of the vector register VR0, and the element #i of the vector register VR1 to an operator 9 at the same time.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10153680A JPS5727363A (en) | 1980-07-24 | 1980-07-24 | Vector data processor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10153680A JPS5727363A (en) | 1980-07-24 | 1980-07-24 | Vector data processor |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5727363A true JPS5727363A (en) | 1982-02-13 |
JPS6120906B2 JPS6120906B2 (en) | 1986-05-24 |
Family
ID=14303156
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10153680A Granted JPS5727363A (en) | 1980-07-24 | 1980-07-24 | Vector data processor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5727363A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61202281A (en) * | 1985-03-05 | 1986-09-08 | Fujitsu Ltd | Pipeline control system |
US5142638A (en) * | 1989-02-07 | 1992-08-25 | Cray Research, Inc. | Apparatus for sharing memory in a multiprocessor system |
US5206952A (en) * | 1990-09-12 | 1993-04-27 | Cray Research, Inc. | Fault tolerant networking architecture |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2019176972A (en) | 2018-03-30 | 2019-10-17 | 美津濃株式会社 | Iron golf club head |
-
1980
- 1980-07-24 JP JP10153680A patent/JPS5727363A/en active Granted
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61202281A (en) * | 1985-03-05 | 1986-09-08 | Fujitsu Ltd | Pipeline control system |
US5142638A (en) * | 1989-02-07 | 1992-08-25 | Cray Research, Inc. | Apparatus for sharing memory in a multiprocessor system |
US5206952A (en) * | 1990-09-12 | 1993-04-27 | Cray Research, Inc. | Fault tolerant networking architecture |
Also Published As
Publication number | Publication date |
---|---|
JPS6120906B2 (en) | 1986-05-24 |
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