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JPS56107616A - Control system for time delay rate of signal - Google Patents

Control system for time delay rate of signal

Info

Publication number
JPS56107616A
JPS56107616A JP1047680A JP1047680A JPS56107616A JP S56107616 A JPS56107616 A JP S56107616A JP 1047680 A JP1047680 A JP 1047680A JP 1047680 A JP1047680 A JP 1047680A JP S56107616 A JPS56107616 A JP S56107616A
Authority
JP
Japan
Prior art keywords
register
signal
time delay
taps
selects
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1047680A
Other languages
Japanese (ja)
Inventor
Masao Takahashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP1047680A priority Critical patent/JPS56107616A/en
Publication of JPS56107616A publication Critical patent/JPS56107616A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
    • H03H7/30—Time-delay networks

Landscapes

  • Pulse Circuits (AREA)

Abstract

PURPOSE:To ensure a simple control for the time delay of signal without giving any complicated operation, by using a register and logical circuit in a control system for the time delay rate of a device such as an electronic computer that incorporates a delay line having several output taps and selects either one of the signals supplied from those output taps. CONSTITUTION:The register 6 (to which the data from the service processor 5 is set) and the output tap selection means A' (AND circuits 7-1-7-4 plus OR circuits 8) that selects one of the signals supplied from the output taps O1-O4 in accordance with the value of the register 6 are provided to the device which incorporates the delay line 4 having the taps O1-O4 and selects either one of the signals supplied from the taps O1-O4. Then a setting is secured for an optional value to the register 6 from other device or own device by a softwear-type means B' (that varies the value which is set to the register 6 from the processor 5). Furthermore the signal A is controlled by the actions of the means A' and B' to obtain the signal B having a necessary degree of time delay.
JP1047680A 1980-01-31 1980-01-31 Control system for time delay rate of signal Pending JPS56107616A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1047680A JPS56107616A (en) 1980-01-31 1980-01-31 Control system for time delay rate of signal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1047680A JPS56107616A (en) 1980-01-31 1980-01-31 Control system for time delay rate of signal

Publications (1)

Publication Number Publication Date
JPS56107616A true JPS56107616A (en) 1981-08-26

Family

ID=11751196

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1047680A Pending JPS56107616A (en) 1980-01-31 1980-01-31 Control system for time delay rate of signal

Country Status (1)

Country Link
JP (1) JPS56107616A (en)

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