JPS56107394A - Semiconductor memory circuit - Google Patents
Semiconductor memory circuitInfo
- Publication number
- JPS56107394A JPS56107394A JP906780A JP906780A JPS56107394A JP S56107394 A JPS56107394 A JP S56107394A JP 906780 A JP906780 A JP 906780A JP 906780 A JP906780 A JP 906780A JP S56107394 A JPS56107394 A JP S56107394A
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- write
- semiconductor memory
- node
- stability
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Static Random-Access Memory (AREA)
Abstract
PURPOSE:To increase the stability of operation of a semiconductor memory circuit, by making the threshold voltages of two sets of drive elements of static cell artificially different values. CONSTITUTION:The threshold value of drive transistors T1, T2 connected with load elements R1, R2 of polycrystal silicon high resistance constituting static memory cell, is changed with artificial processing such as ion platation and the threshold value of the transistor T1 is, e.g., selected lower than T2, the margin of low potential write-in to the node B is increased. No effect is given to the high potential write-in via the transistor T2 to the node A and the memory cell makes stable operation without malfunction. Further, when the digit drive transistor T5 is provided and the digit line level is made low level at write-in, the stability of operation can further be increased.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP906780A JPS56107394A (en) | 1980-01-29 | 1980-01-29 | Semiconductor memory circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP906780A JPS56107394A (en) | 1980-01-29 | 1980-01-29 | Semiconductor memory circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS56107394A true JPS56107394A (en) | 1981-08-26 |
Family
ID=11710258
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP906780A Pending JPS56107394A (en) | 1980-01-29 | 1980-01-29 | Semiconductor memory circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56107394A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5475638A (en) * | 1992-04-30 | 1995-12-12 | Mitsubishi Denki Kabushiki Kaisha | Static random access memory device having a single bit line configuration |
FR2891652A1 (en) * | 2005-10-03 | 2007-04-06 | St Microelectronics Sa | Static random access memory cell, has bistable circuit with two nMOS transistors and two switch transistors having respective threshold voltages, where one threshold voltage is greater than other threshold voltage |
-
1980
- 1980-01-29 JP JP906780A patent/JPS56107394A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5475638A (en) * | 1992-04-30 | 1995-12-12 | Mitsubishi Denki Kabushiki Kaisha | Static random access memory device having a single bit line configuration |
US5572469A (en) * | 1992-04-30 | 1996-11-05 | Mitsubishi Denki Kabushiki Kaisha | Static random access memory device having a single bit line configuration |
US5694354A (en) * | 1992-04-30 | 1997-12-02 | Mitsubishi Denki Kabushiki Kaisha | Static random access memory device having a single bit line configuration |
FR2891652A1 (en) * | 2005-10-03 | 2007-04-06 | St Microelectronics Sa | Static random access memory cell, has bistable circuit with two nMOS transistors and two switch transistors having respective threshold voltages, where one threshold voltage is greater than other threshold voltage |
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