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JPS5651085A - Address selection circuit - Google Patents

Address selection circuit

Info

Publication number
JPS5651085A
JPS5651085A JP12839279A JP12839279A JPS5651085A JP S5651085 A JPS5651085 A JP S5651085A JP 12839279 A JP12839279 A JP 12839279A JP 12839279 A JP12839279 A JP 12839279A JP S5651085 A JPS5651085 A JP S5651085A
Authority
JP
Japan
Prior art keywords
circuit
output terminal
decoder
selection
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP12839279A
Other languages
Japanese (ja)
Other versions
JPS6032913B2 (en
Inventor
Masamichi Asano
Hiroshi Iwahashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP54128392A priority Critical patent/JPS6032913B2/en
Priority to US06/192,203 priority patent/US4447895A/en
Priority to DE3037130A priority patent/DE3037130C2/en
Priority to GB8031956A priority patent/GB2060303B/en
Publication of JPS5651085A publication Critical patent/JPS5651085A/en
Priority to US06493605 priority patent/US4509148B1/en
Priority to GB08313395A priority patent/GB2120036B/en
Publication of JPS6032913B2 publication Critical patent/JPS6032913B2/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4085—Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4087—Address decoders, e.g. bit - or word line decoders; Multiple line decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/08—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements
    • G11C17/10—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM
    • G11C17/12—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM using field-effect devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)

Abstract

PURPOSE:To enable to reduce the number of circuits of decoders and the number of elements, by selecting the output of row line selecting buffer in response to the combination of two sets of decoders. CONSTITUTION:The selection/nonselection of the output at an output terminal 36 of a buffer circuit 23 to row lines are determined by the selection/nonselection of the 1st decoder 21 formed with a depletion type load transistor 24 connected between an output terminal 25 and a power supply VC and with enhancement type transistors 261-26i in parallel connection between the output terminal 25 and ground and the gate of which is fed with address inputs A1-Ai, and the 2nd decoder circuit 22 connected with a depletion type transistor 29 and enhancement type transistor 30 and to which address inputs Ai+1-An are fed. With this constitution, the circuit 21 can commonly be used between rows, thereby enabling to reduce the number of decoder circuits for the address selection circuit and number of components and to decrease the current consumption.
JP54128392A 1979-10-04 1979-10-04 address selection circuit Expired JPS6032913B2 (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP54128392A JPS6032913B2 (en) 1979-10-04 1979-10-04 address selection circuit
US06/192,203 US4447895A (en) 1979-10-04 1980-09-30 Semiconductor memory device
DE3037130A DE3037130C2 (en) 1979-10-04 1980-10-01 Address designation circuit
GB8031956A GB2060303B (en) 1979-10-04 1980-10-03 Semiconductor memory device
US06493605 US4509148B1 (en) 1979-10-04 1983-05-11 Semiconductor memory device
GB08313395A GB2120036B (en) 1979-10-04 1983-05-16 Semiconductor memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP54128392A JPS6032913B2 (en) 1979-10-04 1979-10-04 address selection circuit

Related Child Applications (2)

Application Number Title Priority Date Filing Date
JP62036975A Division JPS63171494A (en) 1987-02-20 1987-02-20 Address selecting circuit
JP62291917A Division JPS63276786A (en) 1987-11-20 1987-11-20 Address selecting circuit

Publications (2)

Publication Number Publication Date
JPS5651085A true JPS5651085A (en) 1981-05-08
JPS6032913B2 JPS6032913B2 (en) 1985-07-31

Family

ID=14983667

Family Applications (1)

Application Number Title Priority Date Filing Date
JP54128392A Expired JPS6032913B2 (en) 1979-10-04 1979-10-04 address selection circuit

Country Status (1)

Country Link
JP (1) JPS6032913B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5922287A (en) * 1982-07-26 1984-02-04 Nec Corp Memory circuit
JPS61144790A (en) * 1984-12-18 1986-07-02 Sharp Corp Address decoder circuit
US6385123B1 (en) * 1999-06-29 2002-05-07 Infineon Technologies Ag Integrated circuit having a decoder unit and an additional input of a decoder unit to determine a number of outputs to be activated

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5922287A (en) * 1982-07-26 1984-02-04 Nec Corp Memory circuit
JPS61144790A (en) * 1984-12-18 1986-07-02 Sharp Corp Address decoder circuit
US6385123B1 (en) * 1999-06-29 2002-05-07 Infineon Technologies Ag Integrated circuit having a decoder unit and an additional input of a decoder unit to determine a number of outputs to be activated

Also Published As

Publication number Publication date
JPS6032913B2 (en) 1985-07-31

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