JPS5570986A - Semiconductor intergrated circuit device - Google Patents
Semiconductor intergrated circuit deviceInfo
- Publication number
- JPS5570986A JPS5570986A JP14419678A JP14419678A JPS5570986A JP S5570986 A JPS5570986 A JP S5570986A JP 14419678 A JP14419678 A JP 14419678A JP 14419678 A JP14419678 A JP 14419678A JP S5570986 A JPS5570986 A JP S5570986A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- power supply
- memory
- matrix
- circuit device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title 1
- 239000011159 matrix material Substances 0.000 abstract 3
- 101100524644 Toxoplasma gondii ROM4 gene Proteins 0.000 abstract 1
- 230000002093 peripheral effect Effects 0.000 abstract 1
- 230000003068 static effect Effects 0.000 abstract 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Static Random-Access Memory (AREA)
Abstract
PURPOSE:To constitute low power consumption, by selectively performing power supply to the memory matrix and other circuit. CONSTITUTION:The memory circuit consisting of the static type RAM memory matrix 2 and its peripheral circuit 3, memory circuit 4 consisting of ROM, and logic circuit 5 are provided. Further, the load of each circuit is constituted with the E/D MIS circuit using depletion type MISFET, the power supply line for the matrix 2, circuit 3, ROM4, and logic circuit 5 is independently provided and the power supply voltages VDD, VDD' are supplied.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14419678A JPS5570986A (en) | 1978-11-24 | 1978-11-24 | Semiconductor intergrated circuit device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14419678A JPS5570986A (en) | 1978-11-24 | 1978-11-24 | Semiconductor intergrated circuit device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5570986A true JPS5570986A (en) | 1980-05-28 |
Family
ID=15356438
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP14419678A Pending JPS5570986A (en) | 1978-11-24 | 1978-11-24 | Semiconductor intergrated circuit device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5570986A (en) |
Cited By (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0089836A3 (en) * | 1982-03-19 | 1985-12-04 | Fujitsu Limited | Static-type semiconductor memory device |
WO2007134281A3 (en) * | 2006-05-15 | 2008-03-13 | Apple Inc | Two levels of voltage regulation supplied for logic and data programming voltage of a memory device |
US7511646B2 (en) | 2006-05-15 | 2009-03-31 | Apple Inc. | Use of 8-bit or higher A/D for NAND cell value |
US7551486B2 (en) | 2006-05-15 | 2009-06-23 | Apple Inc. | Iterative memory cell charging based on reference cell value |
US7568135B2 (en) | 2006-05-15 | 2009-07-28 | Apple Inc. | Use of alternative value in cell detection |
US7613043B2 (en) | 2006-05-15 | 2009-11-03 | Apple Inc. | Shifting reference values to account for voltage sag |
US7639531B2 (en) | 2006-05-15 | 2009-12-29 | Apple Inc. | Dynamic cell bit resolution |
US7639542B2 (en) | 2006-05-15 | 2009-12-29 | Apple Inc. | Maintenance operations for multi-level data storage cells |
US7852690B2 (en) | 2006-05-15 | 2010-12-14 | Apple Inc. | Multi-chip package for a flash memory |
US7911834B2 (en) | 2006-05-15 | 2011-03-22 | Apple Inc. | Analog interface for a flash memory die |
US9042170B2 (en) | 2006-05-15 | 2015-05-26 | Apple Inc. | Off-die charge pump that supplies multiple flash devices |
-
1978
- 1978-11-24 JP JP14419678A patent/JPS5570986A/en active Pending
Cited By (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0089836A3 (en) * | 1982-03-19 | 1985-12-04 | Fujitsu Limited | Static-type semiconductor memory device |
WO2007134281A3 (en) * | 2006-05-15 | 2008-03-13 | Apple Inc | Two levels of voltage regulation supplied for logic and data programming voltage of a memory device |
US7511646B2 (en) | 2006-05-15 | 2009-03-31 | Apple Inc. | Use of 8-bit or higher A/D for NAND cell value |
US7551486B2 (en) | 2006-05-15 | 2009-06-23 | Apple Inc. | Iterative memory cell charging based on reference cell value |
US7568135B2 (en) | 2006-05-15 | 2009-07-28 | Apple Inc. | Use of alternative value in cell detection |
US7613043B2 (en) | 2006-05-15 | 2009-11-03 | Apple Inc. | Shifting reference values to account for voltage sag |
US7639531B2 (en) | 2006-05-15 | 2009-12-29 | Apple Inc. | Dynamic cell bit resolution |
US7639542B2 (en) | 2006-05-15 | 2009-12-29 | Apple Inc. | Maintenance operations for multi-level data storage cells |
US7701797B2 (en) | 2006-05-15 | 2010-04-20 | Apple Inc. | Two levels of voltage regulation supplied for logic and data programming voltage of a memory device |
US7852690B2 (en) | 2006-05-15 | 2010-12-14 | Apple Inc. | Multi-chip package for a flash memory |
US7852674B2 (en) | 2006-05-15 | 2010-12-14 | Apple Inc. | Dynamic cell bit resolution |
US7881108B2 (en) | 2006-05-15 | 2011-02-01 | Apple Inc. | Maintenance operations for multi-level data storage cells |
US7911834B2 (en) | 2006-05-15 | 2011-03-22 | Apple Inc. | Analog interface for a flash memory die |
US8127202B2 (en) | 2006-05-15 | 2012-02-28 | Apple Inc. | Use of alternative value in cell detection |
US8356231B2 (en) | 2006-05-15 | 2013-01-15 | Apple Inc. | Use of alternative value in cell detection |
US9042170B2 (en) | 2006-05-15 | 2015-05-26 | Apple Inc. | Off-die charge pump that supplies multiple flash devices |
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