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JPS5599764A - Mos memory device - Google Patents

Mos memory device

Info

Publication number
JPS5599764A
JPS5599764A JP798479A JP798479A JPS5599764A JP S5599764 A JPS5599764 A JP S5599764A JP 798479 A JP798479 A JP 798479A JP 798479 A JP798479 A JP 798479A JP S5599764 A JPS5599764 A JP S5599764A
Authority
JP
Japan
Prior art keywords
type
substrate
impurity
source
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP798479A
Other languages
Japanese (ja)
Other versions
JPS6410945B2 (en
Inventor
Kuniyuki Hamano
Toshiyuki Oota
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP798479A priority Critical patent/JPS5599764A/en
Publication of JPS5599764A publication Critical patent/JPS5599764A/en
Publication of JPS6410945B2 publication Critical patent/JPS6410945B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells

Landscapes

  • Semiconductor Memories (AREA)

Abstract

PURPOSE:To increase the degree of integration by injecting an impurity layer of conduction type opposite to that of the substrate into either the source or the drain and diffusing an impurity of conduction type same as the substrate and thereby forming a double impurity layers. CONSTITUTION:MOS memory device 301 consists of p-type silicon substrate 302, n-type impurity layer 303, which has been formed by injecting n-type impurity ions on the drain side, p-type impurity layer 304, which has been formed inside it, source 305 and gate oxide film 306, which have been formed by diffusing an n-type impurity, and metal electrodes 307, 308 and 309. By giving a negative potential to substrate 302, a deplection layer is made to extend from the n-type region diffused in source 305 and the drain side. Next, by giving a negative potential to gate electrode 308, positive holes are accumulated on the surface of Si. When the charges held on Si surface 310 are read out, electrode 307 connected to the doubly diffused drain region is used as a digit line.
JP798479A 1979-01-25 1979-01-25 Mos memory device Granted JPS5599764A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP798479A JPS5599764A (en) 1979-01-25 1979-01-25 Mos memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP798479A JPS5599764A (en) 1979-01-25 1979-01-25 Mos memory device

Publications (2)

Publication Number Publication Date
JPS5599764A true JPS5599764A (en) 1980-07-30
JPS6410945B2 JPS6410945B2 (en) 1989-02-22

Family

ID=11680689

Family Applications (1)

Application Number Title Priority Date Filing Date
JP798479A Granted JPS5599764A (en) 1979-01-25 1979-01-25 Mos memory device

Country Status (1)

Country Link
JP (1) JPS5599764A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5311049A (en) * 1991-10-17 1994-05-10 Rohm Co., Ltd. Non-volatile semiconductor memory with outer drain diffusion layer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5311049A (en) * 1991-10-17 1994-05-10 Rohm Co., Ltd. Non-volatile semiconductor memory with outer drain diffusion layer

Also Published As

Publication number Publication date
JPS6410945B2 (en) 1989-02-22

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