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JPS5599747A - Package for semiconductor device - Google Patents

Package for semiconductor device

Info

Publication number
JPS5599747A
JPS5599747A JP713179A JP713179A JPS5599747A JP S5599747 A JPS5599747 A JP S5599747A JP 713179 A JP713179 A JP 713179A JP 713179 A JP713179 A JP 713179A JP S5599747 A JPS5599747 A JP S5599747A
Authority
JP
Japan
Prior art keywords
substrate
metal layer
bonding
lead
bonded
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP713179A
Other languages
Japanese (ja)
Inventor
Kazuo Yudasaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP713179A priority Critical patent/JPS5599747A/en
Publication of JPS5599747A publication Critical patent/JPS5599747A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE:To make it unnecessary to provide a substrate electrode layer on a semiconductor substrate and also make wire bonding for leads unnecessary by bringing a substrate potential supply lead into direct contact with substrate bonding metal layer 11. CONSTITUTION:The inner end of substrate potential supply lead 16 is bent at right angle to the bottom of center depression 10a of base 10 so that it comes into direct contact with substrate bonding metal layer 11 on the bottom of the center depression when it is bonded with molten glass. In this structure, when silicon semiconductor substrate 18, as an IC chip, is bonded to metal layer 11 by using Au-Si eutectic, substrate potential is directly supplied to substrate 18 via lead 16. It is necessary that the inner end of signal transmission lead 14 should be connected to the corresponding electrode layer on substrate 18 by means of bonding wire 20.
JP713179A 1979-01-26 1979-01-26 Package for semiconductor device Pending JPS5599747A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP713179A JPS5599747A (en) 1979-01-26 1979-01-26 Package for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP713179A JPS5599747A (en) 1979-01-26 1979-01-26 Package for semiconductor device

Publications (1)

Publication Number Publication Date
JPS5599747A true JPS5599747A (en) 1980-07-30

Family

ID=11657516

Family Applications (1)

Application Number Title Priority Date Filing Date
JP713179A Pending JPS5599747A (en) 1979-01-26 1979-01-26 Package for semiconductor device

Country Status (1)

Country Link
JP (1) JPS5599747A (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50120577A (en) * 1974-03-08 1975-09-20
JPS5368573A (en) * 1976-11-30 1978-06-19 Mitsubishi Electric Corp Hermetic sealing method of semiconductor device
JPS5582456A (en) * 1978-12-18 1980-06-21 Mitsubishi Electric Corp Semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50120577A (en) * 1974-03-08 1975-09-20
JPS5368573A (en) * 1976-11-30 1978-06-19 Mitsubishi Electric Corp Hermetic sealing method of semiconductor device
JPS5582456A (en) * 1978-12-18 1980-06-21 Mitsubishi Electric Corp Semiconductor device

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