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JPS5566014A - Data transfer system - Google Patents

Data transfer system

Info

Publication number
JPS5566014A
JPS5566014A JP13825578A JP13825578A JPS5566014A JP S5566014 A JPS5566014 A JP S5566014A JP 13825578 A JP13825578 A JP 13825578A JP 13825578 A JP13825578 A JP 13825578A JP S5566014 A JPS5566014 A JP S5566014A
Authority
JP
Japan
Prior art keywords
data
bff0
main body
computer main
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13825578A
Other languages
Japanese (ja)
Inventor
Kyoji Hayashi
Hiroshi Yokoyama
Manjiro Iida
Koichi Saito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP13825578A priority Critical patent/JPS5566014A/en
Publication of JPS5566014A publication Critical patent/JPS5566014A/en
Pending legal-status Critical Current

Links

Landscapes

  • Bus Control (AREA)

Abstract

PURPOSE:To make it possible to reduce the number of interface signals by providing a means which generates a transfer request signal for transfer of the last data strobe. CONSTITUTION:Data of data buffers BFF0 and BFF1 are transferred to a computer main body successively; and when data is set in BFF0 by last data strobe signal DS to complete I/O operations, an I/O device breaks busy signal BSY. At this time, the output from output end Q' of FF, FF1 is applied to the J terminal of FF, FF2 because FF, FF1 is reset, and FF2 is set, and the Q output of FF2 is applied to FF, FF3 through NOR circuit G5, and FF3 is set, thereby transferring transfer request signal REQ from output end Q of FF3 to the computer main body through driver D4. At this time, AND gate G4 is not selected because FF1 is reset, and only zone control signal ZN0 becomes ''1'', thus transferring only eight-bit data of BFF0 to the computer main body.
JP13825578A 1978-11-09 1978-11-09 Data transfer system Pending JPS5566014A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13825578A JPS5566014A (en) 1978-11-09 1978-11-09 Data transfer system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13825578A JPS5566014A (en) 1978-11-09 1978-11-09 Data transfer system

Publications (1)

Publication Number Publication Date
JPS5566014A true JPS5566014A (en) 1980-05-19

Family

ID=15217668

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13825578A Pending JPS5566014A (en) 1978-11-09 1978-11-09 Data transfer system

Country Status (1)

Country Link
JP (1) JPS5566014A (en)

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