[go: up one dir, main page]

JPS6448159A - Data prefetch system - Google Patents

Data prefetch system

Info

Publication number
JPS6448159A
JPS6448159A JP20546587A JP20546587A JPS6448159A JP S6448159 A JPS6448159 A JP S6448159A JP 20546587 A JP20546587 A JP 20546587A JP 20546587 A JP20546587 A JP 20546587A JP S6448159 A JPS6448159 A JP S6448159A
Authority
JP
Japan
Prior art keywords
data
memory
transfer
bytes
transferred
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20546587A
Other languages
Japanese (ja)
Inventor
Shoichi Yoshida
Hidenori Karibe
Hiroshi Matsushita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP20546587A priority Critical patent/JPS6448159A/en
Publication of JPS6448159A publication Critical patent/JPS6448159A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)

Abstract

PURPOSE:To reduce the number of times of access to a memory and to quickly transfer data to an I/O by collectively prefetching bytes, whose number corresponds to the number of local burst transfer bytes, from the memory and successively transferring them to the I/O. CONSTITUTION:Data is transferred between a memory 6 and I/Os 5-1, 5-2, etc. That is, when data which a channel 1 takes out from the memory 6 in the burst mode is transferred to the I/O 5-1, a prefetch flag 2-1 is turned on and the number of all bytes of data transfer is stored as a local burst transfer byte number 2-2. In second and following data transfer, bytes whose number corresponds to the local burst transfer byte number 2-2 are collectively taken out from the memory 6 in response to a data transfer request and are stored in a data buffer 3, and stored data is successively transferred to I/Os 5-1 and 5-2. Thus, the number of times of access to the memory is reduced and data is quickly transferred to I/Os.
JP20546587A 1987-08-19 1987-08-19 Data prefetch system Pending JPS6448159A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20546587A JPS6448159A (en) 1987-08-19 1987-08-19 Data prefetch system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20546587A JPS6448159A (en) 1987-08-19 1987-08-19 Data prefetch system

Publications (1)

Publication Number Publication Date
JPS6448159A true JPS6448159A (en) 1989-02-22

Family

ID=16507316

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20546587A Pending JPS6448159A (en) 1987-08-19 1987-08-19 Data prefetch system

Country Status (1)

Country Link
JP (1) JPS6448159A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0464159A (en) * 1990-07-02 1992-02-28 Fujitsu Ltd Data transfer control system
JP2007500402A (en) * 2003-05-07 2007-01-11 フリースケール セミコンダクター インコーポレイテッド Data processing system with peripheral device access protection

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0464159A (en) * 1990-07-02 1992-02-28 Fujitsu Ltd Data transfer control system
JP2007500402A (en) * 2003-05-07 2007-01-11 フリースケール セミコンダクター インコーポレイテッド Data processing system with peripheral device access protection

Similar Documents

Publication Publication Date Title
JPS6419438A (en) Hot stand-by memory copy system
JPS5717049A (en) Direct memory access controlling circuit and data processing system
EP0366325A3 (en) Variable length cache fill
ES8702678A1 (en) I/O controller for multiple disparate serial memories with a cache.
EP0382358A3 (en) Full address and odd boundary direct memory access controller
JPS6448159A (en) Data prefetch system
JPS5398741A (en) High level recording and processing system
JPS53126828A (en) Storage control unit
TW326512B (en) Pre-charging output peripheral for direct memory access operation
JPS5720831A (en) Local burst transfer controlling system
JPS55146682A (en) Data transfer system
GB2211325A (en) DMA controller
JPS55108030A (en) Data transfer control system
JPS5616256A (en) Disc cash system
JPS5730179A (en) Buffer memory control system
JPS6459441A (en) Cash system
JPS641046A (en) Memory access control system
JPS5697126A (en) Data buffer controling system
JPS6473458A (en) System for controlling access of vector data
JPS5442937A (en) Data input system
JPS6468868A (en) Buffer control system for bus adapter
EP0377969A3 (en) I/o cached computer systems
JPS53116041A (en) System controller
JPS5549749A (en) Microprogram control data processing system
JPS5794974A (en) Buffer memory control system