[go: up one dir, main page]

JPS57211661A - Data transfer system for multiprocessor device - Google Patents

Data transfer system for multiprocessor device

Info

Publication number
JPS57211661A
JPS57211661A JP9540381A JP9540381A JPS57211661A JP S57211661 A JPS57211661 A JP S57211661A JP 9540381 A JP9540381 A JP 9540381A JP 9540381 A JP9540381 A JP 9540381A JP S57211661 A JPS57211661 A JP S57211661A
Authority
JP
Japan
Prior art keywords
cpu
data
bus
signal
cpus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9540381A
Other languages
Japanese (ja)
Other versions
JPS634220B2 (en
Inventor
Hiroshi Itaya
Kenji Nakatsugawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Anritsu Corp
Original Assignee
Anritsu Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Anritsu Corp filed Critical Anritsu Corp
Priority to JP9540381A priority Critical patent/JPS57211661A/en
Publication of JPS57211661A publication Critical patent/JPS57211661A/en
Publication of JPS634220B2 publication Critical patent/JPS634220B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/167—Interprocessor communication using a common memory, e.g. mailbox

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Information Transfer Systems (AREA)

Abstract

PURPOSE:To transfer data between data transmission-side and receiving-side CPUs without paying attention to operations of other CPUs, by accessing data, which is transferred to and held in a mian storage device preliminarily from the data transmission-side CPU, from the data receiving-side CPU by a common bus use permission signal. CONSTITUTION:In case that a CPU 112-0 wants to transfer data immediately to a CPU 112-1, the CPU 112-0 transfers data to a main storage device 13 and transmits the code of the CPU 112-1 to a CPU controlling circuit 114. This circuit 114 transmits a use permission signal of a commom bus 15 to the CPU 112-1. The CPU 112-1 receives this signal to transmit a use request signal of the bus 15 and accesses to the device 13 and takes in immediately data transferred from the cpu 112-0 to the device 13.
JP9540381A 1981-06-22 1981-06-22 Data transfer system for multiprocessor device Granted JPS57211661A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9540381A JPS57211661A (en) 1981-06-22 1981-06-22 Data transfer system for multiprocessor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9540381A JPS57211661A (en) 1981-06-22 1981-06-22 Data transfer system for multiprocessor device

Publications (2)

Publication Number Publication Date
JPS57211661A true JPS57211661A (en) 1982-12-25
JPS634220B2 JPS634220B2 (en) 1988-01-28

Family

ID=14136696

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9540381A Granted JPS57211661A (en) 1981-06-22 1981-06-22 Data transfer system for multiprocessor device

Country Status (1)

Country Link
JP (1) JPS57211661A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS626365A (en) * 1985-07-02 1987-01-13 Nippon Denzai Kogyo Kenkyusho:Kk Multi-processor system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS626365A (en) * 1985-07-02 1987-01-13 Nippon Denzai Kogyo Kenkyusho:Kk Multi-processor system

Also Published As

Publication number Publication date
JPS634220B2 (en) 1988-01-28

Similar Documents

Publication Publication Date Title
EP0111840A3 (en) Access control method for multiprocessor systems
ES8303745A1 (en) Improved system for interrupt arbitration.
JPS57105879A (en) Control system for storage device
EP0927938A4 (en) Data transfer method and device
GB2156113B (en) Microcomputer data processing systems permitting bus control by peripheral processing devices
JPS57105023A (en) Data transfer system
JPS5790740A (en) Information transfer device
ES8102439A1 (en) Data-transfer controlling system.
JPS55153024A (en) Bus control system
DE3277424D1 (en) Coupler for processors
JPS57211661A (en) Data transfer system for multiprocessor device
JPS5622160A (en) Data processing system having additional processor
JPS56147224A (en) Information processor
JPS57111733A (en) Bus conversion system
JPS57150017A (en) Direct memory access system
JPS57162164A (en) Data transfer device
EP0382342A3 (en) Computer system dma transfer
JPS53112625A (en) Bus occupation control system
JPS5674738A (en) Transfer system of display data
JPS54121632A (en) Interruption request system
JPS57211660A (en) Data transfer system for multiprocessor device
JPS5750039A (en) Computer system
JPS5644925A (en) Control system of data processing system
JPS5629732A (en) Bus control system
JPS5515521A (en) Computer combination system