JPS5563837A - Preparation of semiconductor device - Google Patents
Preparation of semiconductor deviceInfo
- Publication number
- JPS5563837A JPS5563837A JP13704078A JP13704078A JPS5563837A JP S5563837 A JPS5563837 A JP S5563837A JP 13704078 A JP13704078 A JP 13704078A JP 13704078 A JP13704078 A JP 13704078A JP S5563837 A JPS5563837 A JP S5563837A
- Authority
- JP
- Japan
- Prior art keywords
- type
- region
- introducing
- depth
- electrical characteristics
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title 1
- 239000012535 impurity Substances 0.000 abstract 3
- 238000000034 method Methods 0.000 abstract 3
- 239000000758 substrate Substances 0.000 abstract 3
- 238000009792 diffusion process Methods 0.000 abstract 2
- 238000005530 etching Methods 0.000 abstract 1
- 238000000926 separation method Methods 0.000 abstract 1
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Bipolar Integrated Circuits (AREA)
Abstract
PURPOSE: To provide a plurality of elements of different electrical characteristics within the same substrate through the same process, without resort to additional process, by eliminating part of a mask used for introducing a first conductive type impurity, and by introducing a second conductive type impurity.
CONSTITUTION: The device is prepared by forming a n+-type embedded layer on a p-type substrate 21, n-type epitaxial layer 24, p-type separation region 25, and then Si oxide film on the entire surface thereof, and thereafter etching it so that oxide films 26b, 26c of different width are partly left in the portion located within the base region to form p+ diffusion layers 27a and 27b. The width to be left behind should be more than two times the depth of p+ diffusion layer. Then, an oxide film 28 is formed and a collector-emitter region is etched. At this juncture, at least part of the oxide films 26b, 26c is removed, and then n-type impurities are introduced to form an emitter which is shallow in depth and low in concentration as compared with other p+-type region. Like these, the plurality of elements having different electrical characteristics can be formed on the same substrate through one process that forms electrodes 32, 33 and 34.
COPYRIGHT: (C)1980,JPO&Japio
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13704078A JPS5563837A (en) | 1978-11-06 | 1978-11-06 | Preparation of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13704078A JPS5563837A (en) | 1978-11-06 | 1978-11-06 | Preparation of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5563837A true JPS5563837A (en) | 1980-05-14 |
Family
ID=15189447
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13704078A Pending JPS5563837A (en) | 1978-11-06 | 1978-11-06 | Preparation of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5563837A (en) |
-
1978
- 1978-11-06 JP JP13704078A patent/JPS5563837A/en active Pending
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