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JPS5557960A - Debugging system - Google Patents

Debugging system

Info

Publication number
JPS5557960A
JPS5557960A JP13193278A JP13193278A JPS5557960A JP S5557960 A JPS5557960 A JP S5557960A JP 13193278 A JP13193278 A JP 13193278A JP 13193278 A JP13193278 A JP 13193278A JP S5557960 A JPS5557960 A JP S5557960A
Authority
JP
Japan
Prior art keywords
memory
address
cpu11
bus
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13193278A
Other languages
Japanese (ja)
Inventor
Soji Nishimura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nissin Electric Co Ltd
Original Assignee
Nissin Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nissin Electric Co Ltd filed Critical Nissin Electric Co Ltd
Priority to JP13193278A priority Critical patent/JPS5557960A/en
Publication of JPS5557960A publication Critical patent/JPS5557960A/en
Pending legal-status Critical Current

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  • Debugging And Monitoring (AREA)

Abstract

PURPOSE: To simplify interruption constitution by using a signal, based on the output of an address comparator circuit, as a bus charnge-over signal.
CONSTITUTION: While CPU11 is executing a program, address comparator circuit 15 makes a comparison between the address value of 1st address bus 14a and a break point and when the both agree each other, coincidence output (a) is outputted make 1st tri-state buffer circuit 19 high in impedance and 1st and 3rd data buses 14a and 14b are mutually insulated to make 2nd tri-state buffer circuit 19 conductive, so that 2nd and 3rd data buses 14b and 14c will mutually connected. Therefore, CPU11 having attained access to memory 12 starts executing the contents of memory address jumping memory 20. At the same time as access to memory 20, CPU11 sends a reset signal C to latch circuit 16 to changing a bus to the original one and then executes the contents of memory 12.
COPYRIGHT: (C)1980,JPO&Japio
JP13193278A 1978-10-25 1978-10-25 Debugging system Pending JPS5557960A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13193278A JPS5557960A (en) 1978-10-25 1978-10-25 Debugging system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13193278A JPS5557960A (en) 1978-10-25 1978-10-25 Debugging system

Publications (1)

Publication Number Publication Date
JPS5557960A true JPS5557960A (en) 1980-04-30

Family

ID=15069574

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13193278A Pending JPS5557960A (en) 1978-10-25 1978-10-25 Debugging system

Country Status (1)

Country Link
JP (1) JPS5557960A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55146621A (en) * 1979-05-02 1980-11-15 Toshiba Corp Handling unit for document and the like
JPS58197553A (en) * 1982-05-12 1983-11-17 Mitsubishi Electric Corp Program monitor
US4819042A (en) * 1983-10-31 1989-04-04 Kaufman Lance R Isolated package for multiple semiconductor power components

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55146621A (en) * 1979-05-02 1980-11-15 Toshiba Corp Handling unit for document and the like
JPS58197553A (en) * 1982-05-12 1983-11-17 Mitsubishi Electric Corp Program monitor
US4819042A (en) * 1983-10-31 1989-04-04 Kaufman Lance R Isolated package for multiple semiconductor power components

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