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JPS5690348A - Interruption control system - Google Patents

Interruption control system

Info

Publication number
JPS5690348A
JPS5690348A JP16800579A JP16800579A JPS5690348A JP S5690348 A JPS5690348 A JP S5690348A JP 16800579 A JP16800579 A JP 16800579A JP 16800579 A JP16800579 A JP 16800579A JP S5690348 A JPS5690348 A JP S5690348A
Authority
JP
Japan
Prior art keywords
interruption
register
signal
processor
processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16800579A
Other languages
Japanese (ja)
Inventor
Shigeru Hashimoto
Yoichi Aoki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP16800579A priority Critical patent/JPS5690348A/en
Publication of JPS5690348A publication Critical patent/JPS5690348A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To execute an unmaskable interruption as to plural events, by providing a register having bits corresponding to plural unmaskable interruption events, and processing them in order by watching the register by a processor.
CONSTITUTION: When the prescribed unit register I0 in the interruption signal register 1a is set by an interruption signal, the interruption signal sets the FF3. An output signal (a) of the FF3 becomes an interruption signal of the processor 5. The processor 5 saves a data in the save area and executes the interruption processing. On the other hand, (a) closes the gate circuit 2. In case of other interruptions I1W In which require the address information, the processor 5 reads them selecting through the gate circuit 7. When the interruption processing has been finished in the processor 5, a processing end signal (b) is generated after the unit register of the register Ia has been corrected through the bas line 8. This signal (b) opens the circuit 2 and also resets FF3. Accordingly, when other interruption signal is set to the register Ia, the FF3 is set.
COPYRIGHT: (C)1981,JPO&Japio
JP16800579A 1979-12-24 1979-12-24 Interruption control system Pending JPS5690348A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16800579A JPS5690348A (en) 1979-12-24 1979-12-24 Interruption control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16800579A JPS5690348A (en) 1979-12-24 1979-12-24 Interruption control system

Publications (1)

Publication Number Publication Date
JPS5690348A true JPS5690348A (en) 1981-07-22

Family

ID=15860028

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16800579A Pending JPS5690348A (en) 1979-12-24 1979-12-24 Interruption control system

Country Status (1)

Country Link
JP (1) JPS5690348A (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4940837A (en) * 1972-08-25 1974-04-17
JPS5232647A (en) * 1975-09-08 1977-03-12 Mitsui Eng & Shipbuild Co Ltd Interruption system of electronic computer
JPS53121439A (en) * 1977-03-31 1978-10-23 Toshiba Corp Interrupt processor

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4940837A (en) * 1972-08-25 1974-04-17
JPS5232647A (en) * 1975-09-08 1977-03-12 Mitsui Eng & Shipbuild Co Ltd Interruption system of electronic computer
JPS53121439A (en) * 1977-03-31 1978-10-23 Toshiba Corp Interrupt processor

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