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JPS5541511A - Micro program control system - Google Patents

Micro program control system

Info

Publication number
JPS5541511A
JPS5541511A JP11382678A JP11382678A JPS5541511A JP S5541511 A JPS5541511 A JP S5541511A JP 11382678 A JP11382678 A JP 11382678A JP 11382678 A JP11382678 A JP 11382678A JP S5541511 A JPS5541511 A JP S5541511A
Authority
JP
Japan
Prior art keywords
register
line
micro
signals
micro instruction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11382678A
Other languages
Japanese (ja)
Inventor
Tadashi Nakanuma
Katsuji Horiguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP11382678A priority Critical patent/JPS5541511A/en
Publication of JPS5541511A publication Critical patent/JPS5541511A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To omit a micro program loader by transmitting micro instructions to a register of a controlled part and receiving them from the register for the purpose of writing and reading them on a control memory unit.
CONSTITUTION: When flip flop (FF) 28 is set by a micro instruction of micro instruction register 23, access for control memory unit 22 is controlled by signals on line i. Then, the micro instruction from a register in controlled part 24 is written or read through signal line f for the address from micro address register 26 outputted from sequencer 21 on a basis of signals on line h. The wirte to the micro instruction register is inhibited by signals on line j, and controlled part 24 is controlled by signals on line k, and micro instruction transmission and receiving between the internal register and control memory unit 22 are executed through line f.
COPYRIGHT: (C)1980,JPO&Japio
JP11382678A 1978-09-16 1978-09-16 Micro program control system Pending JPS5541511A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11382678A JPS5541511A (en) 1978-09-16 1978-09-16 Micro program control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11382678A JPS5541511A (en) 1978-09-16 1978-09-16 Micro program control system

Publications (1)

Publication Number Publication Date
JPS5541511A true JPS5541511A (en) 1980-03-24

Family

ID=14622007

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11382678A Pending JPS5541511A (en) 1978-09-16 1978-09-16 Micro program control system

Country Status (1)

Country Link
JP (1) JPS5541511A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60230238A (en) * 1984-04-27 1985-11-15 Toshiba Corp Microprogram control device
JPS62118478A (en) * 1985-11-19 1987-05-29 Sony Corp Information processor

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60230238A (en) * 1984-04-27 1985-11-15 Toshiba Corp Microprogram control device
JPH0561659B2 (en) * 1984-04-27 1993-09-06 Tokyo Shibaura Electric Co
JPS62118478A (en) * 1985-11-19 1987-05-29 Sony Corp Information processor

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