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JPS5520546A - Peripheral unit controller - Google Patents

Peripheral unit controller

Info

Publication number
JPS5520546A
JPS5520546A JP9292778A JP9292778A JPS5520546A JP S5520546 A JPS5520546 A JP S5520546A JP 9292778 A JP9292778 A JP 9292778A JP 9292778 A JP9292778 A JP 9292778A JP S5520546 A JPS5520546 A JP S5520546A
Authority
JP
Japan
Prior art keywords
peripheral unit
information
output
ram2f
control part
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9292778A
Other languages
Japanese (ja)
Inventor
Kohei Takeno
Hiroyoshi Masaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP9292778A priority Critical patent/JPS5520546A/en
Publication of JPS5520546A publication Critical patent/JPS5520546A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To enable CPU to deliver the output to peripheral unit controller IOC regardless of the operation speed and the interface conditions of the peripheral unit by preparing the comparatively small-capacity RAM into IOC, and thus to increase the process speed of CPU as well as to simplify the monitor program.
CONSTITUTION: CPU1 carries out the output order continuously regardless of the response speed of the peripheral unit, and the output information is written sequentially and every execution of the output order into RAM2f of IOC2 selected at command decoding part 2c. Read/write control part 2g of RAM2f orders the writing and reads out one information reading order by the request given from timing control part 2d. The information thus drawn out is stored temporarily into memory 2a and then delivered to peripheral unit 3 via output driver 2b. Unit 3 gives the ready signal to part 2d when the output of one information completes and then requests the next information. Thus the full information of RAM2f is delivered to the peripheral unit via control part 2g.
COPYRIGHT: (C)1980,JPO&Japio
JP9292778A 1978-07-28 1978-07-28 Peripheral unit controller Pending JPS5520546A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9292778A JPS5520546A (en) 1978-07-28 1978-07-28 Peripheral unit controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9292778A JPS5520546A (en) 1978-07-28 1978-07-28 Peripheral unit controller

Publications (1)

Publication Number Publication Date
JPS5520546A true JPS5520546A (en) 1980-02-14

Family

ID=14068119

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9292778A Pending JPS5520546A (en) 1978-07-28 1978-07-28 Peripheral unit controller

Country Status (1)

Country Link
JP (1) JPS5520546A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57147878U (en) * 1981-03-13 1982-09-17
JPS5945640U (en) * 1982-09-13 1984-03-26 横河電機株式会社 I/O interface circuit
JPS61206060A (en) * 1985-03-09 1986-09-12 Alps Electric Co Ltd Parallel control system for output device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57147878U (en) * 1981-03-13 1982-09-17
JPS5945640U (en) * 1982-09-13 1984-03-26 横河電機株式会社 I/O interface circuit
JPS61206060A (en) * 1985-03-09 1986-09-12 Alps Electric Co Ltd Parallel control system for output device

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