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JPS55133540A - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device

Info

Publication number
JPS55133540A
JPS55133540A JP4012579A JP4012579A JPS55133540A JP S55133540 A JPS55133540 A JP S55133540A JP 4012579 A JP4012579 A JP 4012579A JP 4012579 A JP4012579 A JP 4012579A JP S55133540 A JPS55133540 A JP S55133540A
Authority
JP
Japan
Prior art keywords
film
etching
polycrystalline silicon
silicon
pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4012579A
Other languages
Japanese (ja)
Inventor
Teruaki Fukuda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP4012579A priority Critical patent/JPS55133540A/en
Publication of JPS55133540A publication Critical patent/JPS55133540A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Weting (AREA)

Abstract

PURPOSE:To prevent an unevenness of etching caused by metamorphosis of a polycrystalline silicon by using a nitriding film pattern as an etching mask when etching an impurity-doped polycrystalline silicon film which is provided on a semiconductor substrate. CONSTITUTION:In case of performing an etching treatment of polycrystalline silicon film on a wiring of integrated circuit, a silicon heat oxidation film 2 of approximately 1mum is formed on a silicon substrate 1, and then a crystalline silicon film 3 of about 5,000Angstrom is formed and given a conductivity to the above film by heat diffusion of phosphorus. Subsequently, about 1,000Angstrom of silicon nitriding film 4 is attached to the polycrystalline silicon film 3, and a pattern 4' is formed after silicon nitriding film 4 has been selectively removed using a photo etching. Lastly, a wiring 3 is obtained by giving a plasma etching to the polycrystalline silicon film using the pattern 4 as a mask. Hence, the unevenness of etching can be prevented by eliminating a heat oxidation process of polycrystalline silicon without having no anxiety in metamorphosis.
JP4012579A 1979-04-03 1979-04-03 Manufacturing method of semiconductor device Pending JPS55133540A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4012579A JPS55133540A (en) 1979-04-03 1979-04-03 Manufacturing method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4012579A JPS55133540A (en) 1979-04-03 1979-04-03 Manufacturing method of semiconductor device

Publications (1)

Publication Number Publication Date
JPS55133540A true JPS55133540A (en) 1980-10-17

Family

ID=12572091

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4012579A Pending JPS55133540A (en) 1979-04-03 1979-04-03 Manufacturing method of semiconductor device

Country Status (1)

Country Link
JP (1) JPS55133540A (en)

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