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JPS55107232A - Method of forming pattern of resist layer - Google Patents

Method of forming pattern of resist layer

Info

Publication number
JPS55107232A
JPS55107232A JP1476879A JP1476879A JPS55107232A JP S55107232 A JPS55107232 A JP S55107232A JP 1476879 A JP1476879 A JP 1476879A JP 1476879 A JP1476879 A JP 1476879A JP S55107232 A JPS55107232 A JP S55107232A
Authority
JP
Japan
Prior art keywords
resist layer
plate
defect
layer
resist
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1476879A
Other languages
Japanese (ja)
Inventor
Kazuo Ito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP1476879A priority Critical patent/JPS55107232A/en
Publication of JPS55107232A publication Critical patent/JPS55107232A/en
Pending legal-status Critical Current

Links

Landscapes

  • Preparing Plates And Mask In Photomechanical Process (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

PURPOSE: To form the pattern of a resist layer free of any defect by carrying out a plurality of times of photomechanical process.
CONSTITUTION: When a negative type resist is applied on a Cr plate 5 prepared by forming a Cr film 4 on a glass plate 3, and the plate is exposed and developed to form a resist layer 6, the resist layer has partly a defect d. Accordingly, for example, the plate is processed as a temperature of 130°C for 30 minutes and cooled, and a negative type resist is again applied. Then, the plate is superimposed on the pattern of the first layer 6 with a high accuracy, and exposed and developed to form a resist layer 7. Although a partial defect in the layer 7, the defects d and e are in different positions and therefore a resist layer 8 of a double layer structure has a predetermined pattern and no defect. Consequently, when the Cr plate 5 is subjected to etching, a photomask free of any defect can be obtained.
COPYRIGHT: (C)1980,JPO&Japio
JP1476879A 1979-02-12 1979-02-12 Method of forming pattern of resist layer Pending JPS55107232A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1476879A JPS55107232A (en) 1979-02-12 1979-02-12 Method of forming pattern of resist layer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1476879A JPS55107232A (en) 1979-02-12 1979-02-12 Method of forming pattern of resist layer

Publications (1)

Publication Number Publication Date
JPS55107232A true JPS55107232A (en) 1980-08-16

Family

ID=11870236

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1476879A Pending JPS55107232A (en) 1979-02-12 1979-02-12 Method of forming pattern of resist layer

Country Status (1)

Country Link
JP (1) JPS55107232A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03179350A (en) * 1989-12-07 1991-08-05 Matsushita Electron Corp Reduction stepper and manufacture of semiconductor device using same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03179350A (en) * 1989-12-07 1991-08-05 Matsushita Electron Corp Reduction stepper and manufacture of semiconductor device using same

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