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JPS5494251A - Operation unit for two dimensional orthogonal conversion - Google Patents

Operation unit for two dimensional orthogonal conversion

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Publication number
JPS5494251A
JPS5494251A JP164078A JP164078A JPS5494251A JP S5494251 A JPS5494251 A JP S5494251A JP 164078 A JP164078 A JP 164078A JP 164078 A JP164078 A JP 164078A JP S5494251 A JPS5494251 A JP S5494251A
Authority
JP
Japan
Prior art keywords
row
column
address
constitution
counter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP164078A
Other languages
Japanese (ja)
Inventor
Kunio Nakatsuka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP164078A priority Critical patent/JPS5494251A/en
Publication of JPS5494251A publication Critical patent/JPS5494251A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To enable to perform high speed data processing, by providing the address conversion unit directly coupled with the external memory unit for exclusive use for video information making unnecessary the address calculation by the electronic computer through the adoption of two dimensional address system and executing the data transfer and data conversion without via the computer.
CONSTITUTION: In the operation unit converting the digital video data into two dimensional orthogonal conversion, respectively as to the two dimension, the external memory circuit 3' possible for addressing, controller 7 connected to the electronic computer, address conversion unit 8 connected to the unit 7, primary dimension FET circuit 4, and multiplier 9 are provided. The converter 8 with this constitution, is provided with the row counter 81 representing the row of the coordinate of the processing picture, and the column counter 82 representing the column of the coordinate, and further, the bit inversion row counter 83 inverting the bit constitution of the row are that of the column, and the bit inversion column counter 84 are provided. Moreover, the X axis multiplexers 8x1 to 8x4 and the Y axis multiplexers 8y1 to 8y4 commonly receiving the output of the counters 31 to 34 and designating the two dimensional address, are provided.
COPYRIGHT: (C)1979,JPO&Japio
JP164078A 1978-01-10 1978-01-10 Operation unit for two dimensional orthogonal conversion Pending JPS5494251A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP164078A JPS5494251A (en) 1978-01-10 1978-01-10 Operation unit for two dimensional orthogonal conversion

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP164078A JPS5494251A (en) 1978-01-10 1978-01-10 Operation unit for two dimensional orthogonal conversion

Publications (1)

Publication Number Publication Date
JPS5494251A true JPS5494251A (en) 1979-07-25

Family

ID=11507114

Family Applications (1)

Application Number Title Priority Date Filing Date
JP164078A Pending JPS5494251A (en) 1978-01-10 1978-01-10 Operation unit for two dimensional orthogonal conversion

Country Status (1)

Country Link
JP (1) JPS5494251A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6027069A (en) * 1983-07-22 1985-02-12 Matsushita Electric Ind Co Ltd Fourier transform processor
JPS60204032A (en) * 1984-03-28 1985-10-15 Res Dev Corp Of Japan Pseudo random number generation circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6027069A (en) * 1983-07-22 1985-02-12 Matsushita Electric Ind Co Ltd Fourier transform processor
JPS60204032A (en) * 1984-03-28 1985-10-15 Res Dev Corp Of Japan Pseudo random number generation circuit

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