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JPS54122949A - Analog input unit for computer - Google Patents

Analog input unit for computer

Info

Publication number
JPS54122949A
JPS54122949A JP2991678A JP2991678A JPS54122949A JP S54122949 A JPS54122949 A JP S54122949A JP 2991678 A JP2991678 A JP 2991678A JP 2991678 A JP2991678 A JP 2991678A JP S54122949 A JPS54122949 A JP S54122949A
Authority
JP
Japan
Prior art keywords
file
register
data
signal
analog input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2991678A
Other languages
Japanese (ja)
Inventor
Tadashi Kirisawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP2991678A priority Critical patent/JPS54122949A/en
Publication of JPS54122949A publication Critical patent/JPS54122949A/en
Pending legal-status Critical Current

Links

Landscapes

  • Arrangements For Transmission Of Measured Signals (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

PURPOSE: To ensure the data fetch to computer with a simple circuit constitution, by providing the means fixing the readout data to the output side of the file, when the write-in and readout of register file are duplicated.
CONSTITUTION: The analog input signal of the terminal 1 is fed to the input terminal of the multiplexer 3 and the analog input signal is selected according to the channel number designation signal fed through the signal line 7 from the controller 8 consisting of the control circuit, channel register and decoder. The output signal of the multiplexer 3 is amplified 4 and written in the register file after A/D conversion 5. The write-in is made independently of the A/D conversion data fetch via the data bus 6. When CPU selects a register in the file 11, the data fix signal through the signal line 22 of the unit 8 controls the data fix unit 21 and fixes the output of the register in the file 11. Accordingly, read-in can surely be executed.
COPYRIGHT: (C)1979,JPO&Japio
JP2991678A 1978-03-17 1978-03-17 Analog input unit for computer Pending JPS54122949A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2991678A JPS54122949A (en) 1978-03-17 1978-03-17 Analog input unit for computer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2991678A JPS54122949A (en) 1978-03-17 1978-03-17 Analog input unit for computer

Publications (1)

Publication Number Publication Date
JPS54122949A true JPS54122949A (en) 1979-09-22

Family

ID=12289308

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2991678A Pending JPS54122949A (en) 1978-03-17 1978-03-17 Analog input unit for computer

Country Status (1)

Country Link
JP (1) JPS54122949A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59108938U (en) * 1983-01-05 1984-07-23 株式会社明電舎 data acquisition circuit
JPS59127446A (en) * 1983-01-10 1984-07-23 Akai Electric Co Ltd Address control circuit
JPH05183438A (en) * 1991-12-27 1993-07-23 Nec Corp Analog digital conversion circuit

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59108938U (en) * 1983-01-05 1984-07-23 株式会社明電舎 data acquisition circuit
JPS632921Y2 (en) * 1983-01-05 1988-01-25
JPS59127446A (en) * 1983-01-10 1984-07-23 Akai Electric Co Ltd Address control circuit
JPH05183438A (en) * 1991-12-27 1993-07-23 Nec Corp Analog digital conversion circuit

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