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JPS54101630A - Input/output information check system - Google Patents

Input/output information check system

Info

Publication number
JPS54101630A
JPS54101630A JP736078A JP736078A JPS54101630A JP S54101630 A JPS54101630 A JP S54101630A JP 736078 A JP736078 A JP 736078A JP 736078 A JP736078 A JP 736078A JP S54101630 A JPS54101630 A JP S54101630A
Authority
JP
Japan
Prior art keywords
register
data
stored
storage error
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP736078A
Other languages
Japanese (ja)
Other versions
JPS6042973B2 (en
Inventor
Kazuya Hori
Toshihiko Matsuda
Norio Sogabe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP53007360A priority Critical patent/JPS6042973B2/en
Publication of JPS54101630A publication Critical patent/JPS54101630A/en
Publication of JPS6042973B2 publication Critical patent/JPS6042973B2/en
Expired legal-status Critical Current

Links

Landscapes

  • Techniques For Improving Reliability Of Storages (AREA)
  • Shift Register Type Memory (AREA)
  • Small-Scale Networks (AREA)

Abstract

PURPOSE: To make it possible to detect completely even an I/O register storage error consisting of even bits by comparing data, which is stored in an I/O register and is outputted, with data, which is inputted to the I/O register, in a comparison circuit.
CONSTITUTION: Comparison circuits 301...303 are provided in the output side of I/O registers 201...203 respectively. Now, assuming that R1 I/O register 201 is assigned by the code signal sent through FUN line, this code signal makes AND gate 6 enable through receiver 4 and decoder 5. Next, when the sampling pulse from DTS line is inputted to receiver 3, transfer data is stored in register R1 through gate 6. At the same time, data which is stored in register R1 and is outputted is compared with data of the input side in comparison circuit 301, and the storage error of input information in register 201 is detected. As a result, even an I/O register storage error consisting of even bits can be detected completely.
COPYRIGHT: (C)1979,JPO&Japio
JP53007360A 1978-01-27 1978-01-27 Input/output information check method Expired JPS6042973B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53007360A JPS6042973B2 (en) 1978-01-27 1978-01-27 Input/output information check method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53007360A JPS6042973B2 (en) 1978-01-27 1978-01-27 Input/output information check method

Publications (2)

Publication Number Publication Date
JPS54101630A true JPS54101630A (en) 1979-08-10
JPS6042973B2 JPS6042973B2 (en) 1985-09-26

Family

ID=11663784

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53007360A Expired JPS6042973B2 (en) 1978-01-27 1978-01-27 Input/output information check method

Country Status (1)

Country Link
JP (1) JPS6042973B2 (en)

Also Published As

Publication number Publication date
JPS6042973B2 (en) 1985-09-26

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