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JPS5457928A - Interface unit - Google Patents

Interface unit

Info

Publication number
JPS5457928A
JPS5457928A JP12546877A JP12546877A JPS5457928A JP S5457928 A JPS5457928 A JP S5457928A JP 12546877 A JP12546877 A JP 12546877A JP 12546877 A JP12546877 A JP 12546877A JP S5457928 A JPS5457928 A JP S5457928A
Authority
JP
Japan
Prior art keywords
data
inversion
interface
circuit
timing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12546877A
Other languages
Japanese (ja)
Inventor
Susumu Watanabe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP12546877A priority Critical patent/JPS5457928A/en
Publication of JPS5457928A publication Critical patent/JPS5457928A/en
Pending legal-status Critical Current

Links

Landscapes

  • Detection And Correction Of Errors (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)

Abstract

PURPOSE: To make error detection for data transfer easy and confirm the operation every bit of interface by providing a matching circuit for inversion collating in an inversion data transmission logic and a simple receiving part.
CONSTITUTION: Data ready signals 1R and 2R are transmitted from ready timing circuit 12 of the output interface part to two continuous timing signals 3t and 4t. Meanwhile, in the input interface part, parallel data received by the first timing signal it is stored in receiving data memory 23, and parallel data 2r received by the second timing signal 2t is matched with the output of memory 23 for inversion collation in exclusive logical operation circuit 24. As a result, error detection for data transfer is made easy, and the operation can be confirmed every bit of interface
COPYRIGHT: (C)1979,JPO&Japio
JP12546877A 1977-10-18 1977-10-18 Interface unit Pending JPS5457928A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12546877A JPS5457928A (en) 1977-10-18 1977-10-18 Interface unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12546877A JPS5457928A (en) 1977-10-18 1977-10-18 Interface unit

Publications (1)

Publication Number Publication Date
JPS5457928A true JPS5457928A (en) 1979-05-10

Family

ID=14910825

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12546877A Pending JPS5457928A (en) 1977-10-18 1977-10-18 Interface unit

Country Status (1)

Country Link
JP (1) JPS5457928A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60227545A (en) * 1984-04-26 1985-11-12 Nippon Telegr & Teleph Corp <Ntt> Information transfer method
JPS62282346A (en) * 1986-05-31 1987-12-08 Toshiba Corp Data output circuit
JPH04260537A (en) * 1990-10-17 1992-09-16 Francesco Canziani Sorting device and controlling method therefor

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60227545A (en) * 1984-04-26 1985-11-12 Nippon Telegr & Teleph Corp <Ntt> Information transfer method
JPS62282346A (en) * 1986-05-31 1987-12-08 Toshiba Corp Data output circuit
JPH04260537A (en) * 1990-10-17 1992-09-16 Francesco Canziani Sorting device and controlling method therefor

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