JPH1168532A - Power supply circuit - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To suppress an inrush current by utilizing characteristics of a semiconductor switching element at the time of ON. SOLUTION: When the FET1 is off, the transistor Q
3 is ON, and no electric charge is stored in the capacitor C1. When an ON signal is output from the output terminal P3 of the switch control unit 4, the transistor Q2 turns on, the transistor Q3 turns off, and the transistor Q1 turns on. When the transistor Q3 is turned off and the transistor Q1 is turned on, the delay circuit 31 including the resistor R7 and the capacitor C1 operates, and the transistor Q6 is turned on gently by the delay circuit 31, whereby the voltage applied to the gate of the FET1 becomes gentle. Stand up. Therefore, the on-resistance at the time of switch-on is increased, and the inrush current of the lamp L is suppressed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power supply circuit for controlling power supply from a power supply to a load by turning on and off a semiconductor switching element.

[0002]

2. Description of the Related Art In a load such as a headlamp mounted on an automobile, a large current called an inrush current flows immediately after the start of energization because the filament temperature is low in a non-energized state. Therefore, conventionally, in order to prevent the inrush current from being erroneously detected as an overcurrent, a two-stage overcurrent detection line is provided to provide overcurrent protection for a load such as a lamp that generates an inrush current. (Japanese Patent Publication No. 8-14598).

[0003]

However, in Japanese Patent Publication No. 8-14598, although the inrush current is not erroneously detected as an overcurrent, the inrush current flows through a load such as a lamp. Therefore, the life of the load is reduced.

An object of the present invention is to solve the above-mentioned problem, and an object of the present invention is to provide a power supply circuit that suppresses an inrush current by utilizing the on-time characteristics of a semiconductor switching element.

[0005]

The present invention comprises a control terminal, a first terminal and a second terminal, wherein the first terminal and the second terminal are connected to each other.
A power supply including a semiconductor switching element having a terminal connected in series with a load between a power supply and a ground, and having a connection between the first terminal and the second terminal turned on and off by a control signal input to the control terminal; In the circuit, an ON control circuit for sending an ON signal for turning on the connection between the first terminal and the second terminal to the control terminal as the control signal, the control terminal, the ON control circuit, And a delay circuit for gently rising the ON signal transmitted to the control terminal (claim 1).

According to this configuration, the ON signal sent to the control terminal of the semiconductor switching element gradually rises, so that the connection between the first terminal and the second terminal of the semiconductor switching element slowly turns on. , Thereby suppressing the inrush current to the load.

Further, in the power supply circuit according to the first aspect, the semiconductor switching element is constituted by a field effect transistor having a gate as the control terminal (claim 2).

According to this configuration, by using the field effect transistor as the semiconductor switching element, when the ON signal rises slowly, the ON resistance of the field effect transistor increases when the level of the ON signal is low, so that the load enters the load. The current is surely suppressed.

Further, in the power supply circuit according to claim 1 or 2, the power supply circuit is provided between the delay circuit and the control terminal, and further includes: A PWM control circuit for transmitting a PWM drive signal having a preset duty as the control signal to the control terminal, wherein the PWM drive signal turns on / off the input of the ON signal to the control terminal at the duty. (Claim 3).

According to this configuration, when the ON signal is transmitted to the control terminal, the PWM drive signal having a preset duty is further transmitted as the control signal to the control terminal, and the ON signal is controlled. When the input to the terminal is turned on and off with the above duty, the power supplied to the load is PWM-controlled. At this time, PWM
Since the control circuit is disposed between the delay circuit and the control terminal, the PWM drive signal does not rise slowly due to the influence of the delay circuit.

In particular, when a field-effect transistor is used as a semiconductor switching element, an increase in on-resistance causes an adverse effect such as generation of heat and a reduction in life. Only when the signal is transmitted, when the PWM drive signal is transmitted, the time during which the on-resistance increases is extremely short, and heat generation is suppressed, so that there is no adverse effect.

A control signal has a control terminal, a first terminal, and a second terminal. The first terminal and the second terminal are connected in series with a load between a power supply and a ground, and a control signal input to the control terminal is provided. A power supply circuit including a semiconductor switching element for turning on and off a connection between the first terminal and the second terminal by turning on a connection between the first terminal and the second terminal as the control signal; An ON control circuit for sending an ON signal to the control terminal; and an ON signal between the control terminal and the ON control circuit, the ON signal being sent to the control terminal. , And a PW having a duty previously set as the control signal.
A PWM control circuit for sending an M drive signal toward the control terminal, wherein the PWM drive signal turns on and off the input of the ON signal to the control terminal at the duty.

According to this configuration, an ON control circuit for transmitting an ON signal for turning on the connection between the first terminal and the second terminal of the semiconductor switching element to the control terminal as the control signal, and A PWM control circuit for transmitting a PWM drive signal having a preset duty toward the control terminal, wherein the input of the ON signal to the control terminal is turned on / off at the above-mentioned duty by the PWM drive signal, so that the ON signal and the PWM The drive signals can be generated individually.

[0014]

FIG. 1 is a circuit diagram of an embodiment of a power supply circuit according to the present invention. This power supply circuit controls power supply from a battery B of an automobile to a lamp L, and includes an N-channel MOS-FET (hereinafter simply referred to as “FET”) 1 as a semiconductor switching element, a power supply circuit 2, and a switch drive. The circuit includes a circuit 3, a switch control unit 4, a lamp switch S1, and an operation switch S2.

The battery B is a lead storage battery that outputs a voltage of, for example, 12 V DC, and constitutes a power supply. Lamp L is
Headlamps, tail lamps, stop lamps, and other lamps mounted on vehicles are applied and constitute the load.

The positive terminal of the battery B is connected to the drain (first terminal) of the FET1, the anode of the diode D0 of the switch drive circuit 3, and the power supply circuit 2, and the source (second terminal) of the FET1 is connected via a lamp L. Grounded.

The power supply circuit 2 includes, for example, a three-terminal regulator or a zener diode, generates a constant voltage V _cc (for example, 5 V in the present embodiment) from the output voltage of the battery B, and outputs it from an output terminal.

The switch controller 4 comprises a CPU and the like.
It has input terminals P1, P2 and output terminals P3, P4. The input terminal P1 is grounded via a lamp switch S1, and is pulled up via a resistor.
The input terminal P2 is grounded via the operation switch S2 and is pulled up via a resistor.

The lamp switch S1 is operated externally to turn the lamp L on and off, thereby instructing the lamp L to be turned on and off. The operation switch S2 is operated externally to turn the lamp L off and on. This is for instructing dimming lighting of.

The switch control section 4 controls the turning on and off of the lamp L, and has the following functions. On / off of the lamp switch S1 is determined based on the level of the input signal at the input terminal P1, and a switch signal is output from the output terminal P3. This switch signal is a high-level on signal when the lamp switch S1 is on, and is a low level when the lamp switch S1 is off.

When the lamp switch S1 is on, the on / off state of the operation switch S2 is determined based on the level of the input signal at the input terminal P2. When the operation switch S2 is on, a predetermined frequency of about 0.1 to 1 kHz is used. On-duty (for example, 50% in this embodiment) PWM drive signal
100% on duty when operation switch S2 is off
, Ie, a high level signal is output from the output terminal P4.

The switch driving circuit 3 includes circuit elements such as a resistor, a capacitor, a diode, and a transistor, and applies a voltage to the gate (control terminal) of the FET 1 to turn the FET 1 on and off.

The cathode of the diode D0 is connected to the emitter of the PNP transistor Q1, and the resistor R
1 is connected to the base of the transistor Q1. The base of the transistor Q1 is further connected to the collector of the NPN transistor Q2 via a resistor R2. The collector of the transistor Q2 is further connected to the base of an NPN transistor Q3 via a resistor R5. The base of the transistor Q3 is further grounded via a resistor R6, and the emitter is grounded.

The emitter of the transistor Q2 is grounded,
The base is connected to the output terminal P3 of the switch control unit 4 via a resistor R3, and is grounded via a resistor R4.

The collector of the transistor Q1 is connected to a resistor R7.
To the emitter of the PNP transistor Q6. The emitter of the transistor Q6 is further connected to the collector of the transistor Q3 via a resistor R8, grounded via a capacitor C1, and grounded via a series circuit of resistors R13, R14, R17 and R18. The resistor R7 and the capacitor C1 constitute a delay circuit 31.

The base of the transistor Q6 is connected to a resistor R1.
The connection point of the resistors R14 and R17 is connected to the collector of the NPN transistor Q7.

The base of the transistor Q7 is connected to a resistor R15
Is connected to the output terminal P4 of the switch control section 4 via the resistor R16 and grounded via the resistor R16. The emitter of the transistor Q7 is grounded.

The collector of the transistor Q6 is connected to one electrode of the capacitor C2 and N through a resistor R9.
Connected to the collector of the PN transistor Q4, connected to the other electrode of the capacitor C2 via the resistor R10 and the base of the NPN transistor Q5, connected to one electrode of the capacitor C3 via the resistor R11 and the base of the transistor Q4, The resistor R12 is connected to the other electrode of the capacitor C3 and the collector of the transistor Q5, and is connected to the anode of the diode D1.

The emitters of the transistors Q4 and Q5 are grounded, and the base of the transistor Q4 is further connected to the output terminal P4 of the switch control section 4 via a capacitor C5. The resistors R9, R10, R11, R12, the capacitors C2, C3 and the transistors Q4, Q5 constitute a multivibrator oscillation circuit.

The cathode of the diode D1 is connected to the anode of the diode D2 and the capacitor C4
Is connected to the other electrode of the capacitor C3. The cathode of the diode D2 is connected to the gate of the FET 1 via the resistor R19A.

The base of the NPN transistor Q8 is a resistor R
The emitter is grounded, and the collector is connected to the gate of FET1 via a resistor R19B.

Next, the operation will be described with reference to FIGS. FIG. 2 is a timing chart for explaining the effect of reducing the inrush current by the delay circuit 31.

In FIG. 1, in a steady state where the lamp switch S1 is off, the output terminal P3 of the switch control section 4 is at a low level, so that the transistor Q2 is off.

Here, the resistance values R ₁ , R ₂ , R ₅ , R ₆ of the resistors R ₁ , R ₂ , R ₅ , R ₆ are R ₁ ≪R ₅ <R ₆ , R ₂ ≪R ₅
When the transistor Q2 is off, the base-emitter voltage of the transistor Q1 is designed to be 0.6 V or less.

Therefore, the transistor Q1 is turned off, so that no electric charge is stored in the capacitor C1.

Lamp switch S1 and operation switch S2
Is turned on, a high-level ON signal is output from the output terminal P3 of the switch control unit 4, and a P with an on-duty of 50% is output from the output terminal P4 as shown in FIG.
The WM drive signal is output.

Returning to FIG. 1, this ON signal causes the resistance R
3, the transistor Q2 is turned on. When the transistor Q2 is turned on, the transistor Q3 is turned off and the transistor Q1 is turned on.

When the transistor Q3 is turned off and the transistor Q1 is turned on, the delay circuit 31 composed of the resistor R7 and the capacitor C1 operates. By the action of the delay circuit 31, the base current gradually passes through the resistors R13, R14, R17 and R18. , The transistor Q6 is slowly turned on.

When the transistor Q6 is slowly turned on, the multivibrator oscillation circuit starts oscillating slowly, and the anode potential of the diode D1 is connected to the other electrode side of the capacitor C3 (point X in FIG. 1). A pulse voltage of a level equal to

Then, by the action of the capacitor C4,
By raising the potential of the electrode on the side opposite to the point X of the capacitor C4 by this pulse voltage, the voltage level on the cathode side of the diode D1 becomes almost twice as high as that on the anode side. R19A
Is applied to the gate of FET1 to turn on FET1. That is, the multivibrator oscillation circuit and the capacitor C4 constitute a charge pump circuit 32 for driving the FET1.

As described above, by connecting the resistor R19A to the output side of the charge pump circuit 32, the resistor R1
9A and the capacitance component of the gate of the FET1 form a CR circuit, which makes the rise of the voltage signal applied to the gate of the FET1 somewhat gentle.
The level of noise generated when the FET 1 is turned on can be reduced.

The switch control unit 4 and the transistor Q
1, Q2, Q6 and the charge pump circuit 32 constitute an ON control circuit, and the output terminal P of the switch control unit 4
The function of turning on the FET 1 by the ON signal output from the switch 3 is achieved.

Note that diodes D1 and D2 prevent current from flowing backward due to the voltage applied to the gate of FET1.

On the other hand, when the PWM drive signal output from the output terminal P4 of the switch control section 4 is at a high level, the base current is supplied via the resistor R15, and the transistor Q7 is turned on. The base current is bypassed by transistor Q8.
Turns off. When the transistor Q8 is off, the voltage generated by the charge pump circuit 32
And the FET1 is turned on.

On the other hand, when the PWM drive signal is at a low level, the transistor Q7 is turned off, so that a base current is supplied through the resistors R13, R14 and R17, and the transistor Q8 is turned on. When the transistor Q8 is turned on, the voltage applied to the gate of the FET1 is dropped to the ground via the resistor R19B and the transistor Q8, so that the FET1 is turned off.

As described above, the switch control section 4 and the transistors Q7 and Q8 constitute a PWM control circuit.
PWM output from output terminal P4 of switch control unit 4
It has a function of turning on / off the FET 1 by a drive signal.

Thus, the amount of light emitted from the lamp L can be controlled. For example, if a PWM drive signal with a 50% duty is output, the lamp L can be dimly lit, and if a PWM drive signal with a 100% on duty is output, the lamp L can be lit with a full light quantity.

For example, when the tail lamp is turned on 50
% And the on-duty of the stop lamp are set to 100%, the same filament can be shared.
In this case, when the tail lamp is turned on, the lamp switch S1 and the operation switch S2 are turned on. When the stop lamp is turned on, that is, when the brake pedal (not shown) is operated, the lamp switch S1 is turned on and the operation is performed. What is necessary is just to comprise so that switch S2 may be turned off.

As described above, according to the present embodiment, by providing the delay circuit 31 for slowly raising the high-level switch signal output from the output terminal P3 of the switch control section 4, ie, the ON signal, the FET 1 The rise of the voltage applied to the gate can be made gentle,
This makes it possible to increase the on-resistance of the FET 1 when it is on.

Accordingly, as shown in FIG. 2, the level of the rush current of the load current I _L flowing through the lamp L can be reduced as compared with the case where the delay circuit 31 is not provided, thereby extending the life of the lamp L. Can be planned.

On the other hand, the delay circuit 31 is controlled by the PWM drive signal.
Transistor Q7 disposed between the gate of FET1
Is turned on and off, so that the delay circuit 31 does not operate in the second and subsequent pulse signals of the PWM drive signal, and the on / off of the FET 1 is performed normally without delay.

Therefore, if the level of the voltage applied to the gate of the FET 1 is not sufficiently high, the on-resistance of the FET 1 may increase to generate heat, thereby shortening the life of the FET 1. Is suppressed only at the time of the rise of the ON signal, that is, at the time of the first pulse signal output of the PWM drive signal. Since the normal and fast rising gate voltage is applied after the second time, the above-described operation is suppressed. Can be prevented.

In the second and subsequent pulse signals of the PWM drive signal, since the filament temperature of the lamp L is sufficiently increased by the first energization, the delay circuit 3
Even without the action of 1, the inrush current level does not increase.

As described above, according to the present embodiment, the ON control circuit for driving the FET 1 by the ON signal for turning on the lamp L, and the PWM control circuit for turning on and off the FET 1 by the PWM driving signal for dimming the lamp L Are separately provided and the delay circuit 31 is provided between the ON control circuit and the PWM control circuit.
The level of the rush current flowing into the lamp L can be reduced without reducing the life of the FET 1.

FIG. 3 is a circuit diagram of a modification of the above embodiment. In this modification, the switch drive circuit 3 further includes a reception control unit 33, and the switch control unit 4 includes an output terminal P5 instead of the output terminals P3 and P4. The reception control unit 33 includes an input terminal P11 and output terminals P12 and P1.
3, the output terminal P12 is connected to the base of the transistor Q2 via the resistor R3, and the output terminal P13 is connected to the base of the transistor Q7 via the resistor R15.

The output terminal P5 of the switch control unit 4
And the input terminal P11 of the reception control unit 33 are connected by one signal line W.

The switch control section 4 has the following functions: It is determined whether the lamp switch S1 is on or off. When the lamp switch S1 is turned on, a predetermined on-duty (for example, 50% in this modification) at a predetermined frequency (for example, 5 kHz in this modification) is output from the output terminal P5. The pulse signal is output continuously for a predetermined number of times (for example, three times in this modification).

After the output of the pulse signal three times, it is determined whether the operation switch S2 is on or off. When the operation switch S2 is on, a predetermined frequency (for example, 100 Hz in this modification) is used.
At predetermined on-duty (for example, 10% in this modification)
When the operation switch S2 is off, a PWM drive signal having an on-duty of 100%, that is, a high-level signal is output from the output terminal P5.

When the lamp switch S1 is switched from on to off, a pulse signal having a predetermined on-duty (for example, 50% in this modification) at a predetermined frequency (for example, 5 kHz in this modification) is output from the output terminal P5 a predetermined number of times. (For example, three times in the present modification), continuous output is performed.

The reception control unit 33 is a decoder that outputs a predetermined output signal from the output terminals P12 and P13 based on an input signal to the input terminal P11, and has the following functions.

Based on the input signal to the input terminal P11, it is determined that a pulse signal having a frequency of 5 kHz and an on-duty of 50% has been input three times in succession. The same signal as the signal input to P11 is output from output terminal P13, and a high-level signal is output from output terminal P12.

While the high level signal is being output from the output terminal P12, the frequency is determined based on the input signal to the input terminal P11.
It is determined that a pulse signal of 5 kHz and 50% on-duty has been input three times in succession. If the input of this pulse signal is determined, the output signals from the output terminals P12 and P13 are lowered to a low level.

Next, the operation will be described with reference to FIGS. FIG. 4 shows the lamp switch S1 and the operation switch S.
6 is a timing chart illustrating output signals of respective terminals corresponding to the state of FIG.

First, the state where the operation switch S2 is off will be described. When the lamp switch S1 at time point t ₁ is turned on, the frequency 5 kHz (cycle 0.2 ms), the on-duty 5
The pulse signal of 0% is output from the output terminal P5 of the switch control unit 4 three times in succession. Next, the operation switch S
Because 2 is off, the high level signal from t ₂ time is output from the output terminal P5.

[0065] On the other hand, the reception control unit 33, the lamp switch S1 is judged to have been turned on when the pulse signal of 3 times to the input terminal P11 is input, the output terminal of the switch control unit 4 t ₂ time A high-level signal is output from the output terminal P12 in synchronization with the output signal of P5, and the same signal as the input signal from the output terminal P5 to the input terminal P11, that is, the high-level signal is output from the output terminal P1.
3 is output.

Next, when the lamp switch S1 is turned off at time t ₃ , a pulse signal having a frequency of 5 kHz (period: 0.2 ms) and an on-duty of 50% is continuously output from the output terminal P5 of the switch controller 4 three times. Is done.

Then, in the reception control section 33, at time t ₄ when the three pulse signals are input, the lamp switch S1 is turned on.
Is turned off, the output terminals P12, P1
3 is dropped to a low level.

Next, the state where the operation switch S2 is on will be described. When the lamp switch S1 and the operation switch S2 is turned on at t ₁₁ the time, frequency 5 kHz (cycle 0.2m
s) A pulse signal with an on-duty of 50% is continuously output from the output terminal P5 of the switch control unit 3 three times. Then, since the operation switch S2 is on, the t ₁₂ time at a frequency 100 Hz (period 10 ms) on-duty of 10% P
The WM drive signal is output from the output terminal P5.

[0069] On the other hand, the reception control unit 33, the lamp switch S1 is judged to have been turned on when the pulse signal of 3 times to the input terminal P11 is input, the output terminal of the switch control unit 4 t ₂ time A high level signal is output from the output terminal P12 in synchronization with the output signal of P5, and the same signal as the input signal from the output terminal P5 to the input terminal P11, that is, the PWM drive signal is output from the output terminal P1.
3 is output.

[0070] Next, t ₁₃ when the lamp switch S1 and the operation switch S2 at the time is turned off, the frequency 5 kHz (cycle 0.2 ms) from the output terminal P5 of the switch control unit 4, the on-duty of 50% of the pulse signal is three times Output continuously.

[0071] Then, the reception control unit 33, the lamp switch S1 three times t ₁₄ when a pulse signal is input
Is turned off, the output terminals P12, P1
3 is dropped to a low level.

As described above, in the present modification, based on the signal transmitted from the switch control unit 4 via the signal line W,
An ON signal output to the transistor Q2 forming the ON control circuit, and a transistor Q7 forming the PWM control circuit
The switch control circuit 3 is provided with the reception control unit 33 for separating and transmitting the PWM drive signal to be output to the switch drive circuit 3, so that the signal line W connecting the switch control unit 4 and the switch drive circuit 3 can be saved. Can be planned.

Thus, the number of parts can be reduced and the weight of the vehicle can be reduced. In particular, a large effect can be obtained when the printed circuit board on which the switch control section 4 is provided and the printed circuit board on which the switch drive circuit 3 is provided are separated.

The present invention is not limited to the load of the lamp L, but can be applied to a load that generates an inrush current at the start of energization, such as a motor.

[0075]

As described above, according to the present invention,
Since the ON signal sent to the control terminal of the semiconductor switching element is caused to rise slowly, the connection between the first terminal and the second terminal of the semiconductor switching element can be slowly turned on. As a result, inrush current to the load can be suppressed.

In addition, since the semiconductor switching element is constituted by a field effect transistor having a gate as a control terminal, when the ON signal rises slowly, the ON resistance of the field effect transistor increases when the level of the ON signal is low. Rush current to the power supply can be reliably suppressed.

Further, a PWM control circuit is provided between the delay circuit and the control terminal, and when the ON signal is transmitted to the control terminal, the PWM signal having a duty set in advance as a control signal is further provided. A drive signal is transmitted to the control terminal, and the input of the ON signal to the control terminal is turned on / off by the PWM drive signal at the above-mentioned duty, whereby the power supplied to the load can be PWM-controlled, and the PWM drive signal can be controlled. Can be prevented from rising slowly due to the influence of the delay circuit, thereby preventing the semiconductor switching element from being adversely affected.

An ON control circuit for transmitting, to the control terminal, an ON signal for turning on the connection between the first terminal and the second terminal of the semiconductor switching element as a control signal;
A PWM control circuit for transmitting a PWM drive signal of a preset duty as a control signal toward the control terminal, and an input to the control terminal of an ON signal by the PWM drive signal is turned on and off at the duty. An ON signal and a PWM drive signal can be separately generated to control power supply to a load.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of an embodiment of a power supply circuit according to the present invention.

FIG. 2 is a timing chart for explaining an effect of reducing a rush current by a delay circuit.

FIG. 3 is a circuit diagram of a modification of the embodiment.

FIG. 4 is a timing chart showing output signals of respective terminals corresponding to states of respective switches.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 FET 2 Power supply circuit 3 Switch drive circuit 31 Delay circuit 32 Charge pump circuit 33 Reception control part 4 Switch control part B Battery L Lamp

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Takashi Hoshino 1-7-10 Kikuzumi, Minami-ku, Nagoya-shi, Aichi Pref.

Claims (4)

[Claims] 1. A control signal having a control terminal, a first terminal, and a second terminal, wherein the first terminal and the second terminal are connected in series with a load between a power supply and a ground, and input to the control terminal. A power supply circuit including a semiconductor switching element for turning on and off a connection between the first terminal and the second terminal by turning on a connection between the first terminal and the second terminal as the control signal; An on-control circuit for sending an on-signal to the control terminal; and an on-signal provided between the control terminal and the on-control circuit for gradually rising the on-signal sent to the control terminal. A power supply circuit comprising: 2. The power supply circuit according to claim 1, wherein
A power supply circuit, wherein the semiconductor switching element is constituted by a field-effect transistor having a gate as the control terminal. 3. The power supply circuit according to claim 1, wherein the power supply circuit is provided between the delay circuit and the control terminal.
When the ON signal is transmitted to the control terminal, a PWM drive signal having a preset duty as the control signal is further transmitted to the control terminal.
A power supply circuit comprising a WM control circuit, wherein the PWM drive signal turns on / off an input of the ON signal to the control terminal at the duty. 4. A control signal having a control terminal, a first terminal, and a second terminal, wherein the first terminal and the second terminal are connected in series with a load between a power supply and a ground, and are input to the control terminal. A power supply circuit including a semiconductor switching element for turning on and off a connection between the first terminal and the second terminal by turning on a connection between the first terminal and the second terminal as the control signal; An ON control circuit for sending an ON signal to the control terminal; and an ON signal between the control terminal and the ON control circuit, the ON signal being sent to the control terminal. , And a PWM of a duty preset as the control signal.
A PWM control circuit for sending a drive signal toward the control terminal, wherein the PWM drive signal turns on and off the input of the ON signal to the control terminal with the duty. circuit.