JP2004147405A - Vehicle power control device - Google Patents

Abstract

A vehicle power control device capable of suppressing generation of noise without increasing power loss.
A power control device for a vehicle that performs PWM control on a DC voltage output from a battery power source to drive a load 2 such as a lamp mounted on a vehicle, is interposed between the load 2 and a power source, An electronic switch FET1 for switching on / off of a power supply voltage, a charge / discharge capacitor C1, and a first charge / discharge circuit 3 for switching charge / discharge of the capacitor C1 according to a PWM signal. The terminal voltage is supplied to the electronic switch FET1 to turn on and off the electronic switch FET, and the first charge / discharge circuit 3 charges the capacitor C1 at the leading edge (rising portion) of the PWM signal, and outputs the PWM signal. The capacitor C1 is discharged at the trailing edge (falling portion).
[Selection diagram] Fig. 1

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a vehicle power control device that controls power supply to a load mounted on a vehicle, and more particularly to a technique for reducing the generation of noise.
[0002]
[Prior art]
For example, for a lamp load or a motor load mounted on a vehicle, a voltage supplied from a battery mounted on the vehicle is converted into a desired voltage by PWM control and supplied to each load.
[0003]
In a control circuit that drives a lamp load using such PWM control, a change in the current flowing through the load occurs, so that there is a problem that noise is generated where the time rate of change of the current is large.
[0004]
Therefore, as described in Japanese Patent Application Laid-Open No. 9-204231 (hereinafter, referred to as Patent Document 1), a capacitor is disposed at the gate of a switching MOS-FET to reduce the time change of the gate voltage. Thus, a method of mitigating a sudden change in current and preventing generation of noise has been proposed.
[0005]
[Patent Document 1]
JP-A-9-204231 (FIG. 1)
[0006]
[Problems to be solved by the invention]
FIG. 10 is a characteristic diagram showing changes in the PWM signal, the gate voltage VG of the MOS-FET, the source voltage VS, and the load current IL when the method described in Patent Document 1 is used. After the voltage exceeds the operating threshold voltage Vth of the MOS-FET, the voltage VG rises smoothly (parts with reference numerals p1 and p2), which causes a problem that the power loss of the MOS-FET increases. In addition, since it is necessary to provide a large radiator, there is a problem that the size and cost of the device are increased.
[0007]
SUMMARY OF THE INVENTION The present invention has been made to solve such a conventional problem, and an object thereof is to provide a power control apparatus for a vehicle capable of suppressing generation of noise without increasing power loss. Is to provide.
[0008]
[Means for Solving the Problems]
In order to achieve the above object, an invention according to claim 1 of the present application is directed to a vehicular power control device that drives a load mounted on a vehicle by performing PWM control on a DC voltage output from a power supply. , Or between a load and ground, an electronic switch for turning on / off the power supply voltage, a first capacitor for charging / discharging, and charging / discharging the capacitor in response to a PWM signal. And a first charging / discharging circuit for switching the electronic switch. The first charging / discharging circuit supplies a terminal voltage of the first capacitor to the electronic switch to turn on / off the electronic switch. The first capacitor is charged at a leading edge of the PWM signal, and the first capacitor is discharged at a trailing edge of the PWM signal.
[0009]
The invention according to claim 2 is characterized in that the electronic switch is a field-effect transistor, and applies a terminal voltage of the first capacitor to a gate of the field-effect transistor.
[0010]
According to a third aspect of the present invention, a buffer circuit is provided between the first charge / discharge circuit and the electronic switch.
[0011]
The invention according to claim 4 further comprises a comparing means for comparing a gate voltage of the field effect transistor with a reference voltage, wherein one end of the first capacitor is connected to an output end of the first charge / discharge circuit. The other end is connected to the output end side of the comparing means, and when the comparing means determines that the gate voltage is higher than the reference voltage, charging / discharging of the first capacitor is stopped. When the gate voltage is determined to be lower than the reference voltage, the first capacitor can be charged and discharged.
[0012]
The invention according to claim 5 is characterized in that a Zener diode is interposed between the output terminal of the comparing means and the first capacitor.
[0013]
According to a sixth aspect of the present invention, a second capacitor and a second charge / discharge circuit are provided at a stage preceding the first charge / discharge circuit, and the second charge / discharge circuit receives a slow start signal. In this case, the output signal level is gradually increased by charging the second capacitor, and the output signal level is controlled so as to reach a peak value.
[0014]
The invention described in claim 7 is characterized in that a Zener diode is arranged on a path for charging the second capacitor.
[0015]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a schematic configuration diagram showing a power control device according to a first embodiment of the present invention, and FIG. 2 is a specific circuit configuration diagram.
[0016]
As shown in FIG. 1, the power control device 1 is interposed between a load 2 such as a headlight mounted on a vehicle, a battery supplying a DC voltage of 12 volts, and the load 2, and is controlled by PWM control. An electronic switch FET1 performs switching for supplying desired power to the load 2, and a charge / discharge circuit 3 for charging / discharging a PWM signal having a predetermined duty ratio. The electronic switch FET1 is configured by a MOS-FET.
[0017]
Further, a buffer circuit 4 is provided between the charging / discharging circuit 3 and the gate of the electronic switch FET1, and alleviates a sudden change in the voltage supplied to the gate at rising and falling portions of the PWM. Then, the boosting circuit 5 that supplies the boosted voltage VP to the charging / discharging circuit 3 and the buffer circuit 4, the gate voltage VG of the electronic switch FET1, and a predetermined reference voltage Vref are compared. A comparator 6 for outputting to the charge / discharge circuit 3 via the Zener diode ZD1 and the capacitor C1.
[0018]
As shown in FIG. 2, the charge / discharge circuit 3 includes transistors Q1 to Q4, Q9 to Q11, a current source CC1, and a resistor R1. Transistors Q1-Q4 form a current mirror, and transistors Q9 and Q10 also form a current mirror.
[0019]
The buffer circuit 4 includes transistors Q5 to Q8, diodes D1 and D2, and resistors R2 to R4. The transistors Q5 and Q7 are emitter followers.
[0020]
FIG. 3 is a circuit diagram showing a specific configuration of the booster circuit 5. As shown in FIG. 3, the booster circuit 5 includes an oscillator 7, diodes D10 and D11, and capacitors C10 and C11. Then, the battery voltage is boosted to a desired voltage.
[0021]
Next, the operation of the power control device 1 according to the present embodiment configured as described above will be described.
[0022]
The collector current of transistor Q1 is determined by current source CC1. Therefore, the collector currents of the transistors Q2, Q3, and Q4 become substantially equal to CC1 by the action of the current mirror.
[0023]
When the PWM input is at the L level, the transistor Q11 is turned off, so that the collector currents of the transistors Q2 and Q3 flow through the transistor Q10, and the collector current of the transistor Q10 becomes 2 × CC1. Therefore, the collector current of the transistor Q9 also becomes 2 × CC1 by the action of the current mirror, and the collector current of the transistor Q4 is CC1, so that the electric charge charged in the capacitor C1 is discharged by the difference between the currents. .
[0024]
Next, when the PWM input goes to the H level, the transistor Q11 turns on, and the collector currents of the transistors Q2 and Q3 flow through the transistor Q11, so that the transistor Q9 turns off. Therefore, the collector current CC1 of the transistor Q4 flows into the capacitor C1, and the capacitor C1 is charged.
[0025]
As a result, the collector voltage VC1 (terminal voltage of the first capacitor) of the transistor Q4 changes to be at the L level when the PWM input is at the L level, and to be at the H level when the PWM input is at the H level.
[0026]
The voltage VC1 is buffered by the transistors Q6 and Q8 and the emitter followers Q5 and Q7 of the buffer circuit 4 and supplied to the gate of the electronic switch FET1. The current Igsource in the flowing direction from the buffer circuit 4 is limited to approximately R2 × Vbe6 by the resistor R2 and the transistor Q6. Here, Vbe6 is a forward voltage between the base and the emitter of the transistor Q6.
[0027]
On the other hand, the current Igsink flowing into the buffer 4 is limited to approximately R3 × Vbe8 by the resistor R3 and the transistor Q8. Here, Vbe8 is a forward voltage between the base and the emitter of the transistor Q8. Here, the diodes D1 and D2 are provided for stabilizing the circuit operation. The resistor R4 is for pulling down the gate and has a larger value than the resistor R3.
[0028]
When the gate voltage VG of the electronic switch FET1 is lower than the reference voltage Vref (VG <Vref), the output signal becomes L level, and when the gate voltage VG is higher than the reference voltage Vref (VG ≧ Vref), The output signal goes high. Therefore, when VG <Vref, the capacitor C1 can be charged and discharged, and when VG ≧ Vref, the capacitor C1 cannot be charged and discharged.
[0029]
It is also possible to provide the comparator 6 with hysteresis so as to change Vref at the time of rising and falling.
[0030]
Hereinafter, changes in each signal will be described with reference to the flowchart shown in FIG. In the figure, (a) is a PWM input signal, (b) is a voltage VC1, (c) is a gate voltage VG of the electronic switch FET1, and (d) is an output signal of the comparator 6 (L level on, H level off). (E) shows the source voltage of the electronic switch FET1, and (f) shows the load current IL.
[0031]
When the PWM input is at the L level, as described above, the charging / discharging circuit 3 is in the discharging state, and VC1 is substantially 0 volt. At this time, since the gate voltage VG of the electronic switch FET1 is also 0 volt, the electronic switch FET1 is turned off, and the load current IL is zero.
[0032]
When the PWM input goes high at the timing of time t1, charging of the capacitor C1 is started by the above-described operation. At this time, since the Zener diode ZD1 is provided, the voltage VC1 increases according to the following equation (1).
[0033]
VC1 = Vzd1 + CC1 × Tpwm / C1 (1)
Here, Vzd1 is a voltage drop due to the Zener diode diode ZD1, and Tpwm is an elapsed time from when the PWM input becomes H level.
[0034]
Further, the voltage VG is substantially (VC1-VD1-Vbe5). Here, Vbe5 is a forward voltage between the base and the emitter of the transistor Q5.
[0035]
Then, at time t2, when the voltage VG exceeds the operation threshold voltage Vth of the electronic switch FET1, the value of the source voltage VS of the electronic switch FET1 becomes VG−Vth, and the electronic switch FET1 is turned on. The load current IL flows. At this time, the voltage applied to the load 2 slowly rises with the slope shown in the above equation (1). As a result, the rate of change of the load current IL becomes a small value.
[0036]
Thereafter, at time t3, when the voltage VG exceeds the reference voltage Vref, the output signal of the comparator 6 is inverted and becomes the H level. As a result, the capacitor C1 cannot be charged, so that the voltage VC1 rises rapidly, and the voltage VC1 becomes substantially equal to the output voltage VP of the booster circuit 5.
[0037]
Since the buffer circuit 4 charges the gate capacitance of the electronic switch FET1 with the current Igsource (= R2 × Vbe6) in the flowing direction, the gate voltage VG rises with a substantially constant slope, and the source voltage VS and the load current IL also increase. Follow and rise.
[0038]
Thereafter, at time t4, when the gate voltage VG exceeds the battery voltage VBATT, the value of the source voltage VS settles to the value of VBATT-RDSon × IL. Here, RDSon is the ON resistance of the electronic switch FET1.
[0039]
At time t5, when the PWM input goes to L level, the charge / discharge circuit 3 starts discharging, but since the output of the comparator 6 remains at H level (OFF), the voltage stored in the capacitor C1 becomes Not discharged. Therefore, voltage VC1 drops sharply until gate voltage VG matches reference voltage Vref. Here, the current for discharging the gate charge of the electronic switch FET1 is limited by Igsink (= R3 × Vbe8). Here, Vbe5 is a forward voltage between the base and the emitter of the transistor Q5.
[0040]
At time t6, when the gate voltage VG becomes lower than the reference voltage Vref, the output signal of the comparator 6 goes low (ON). At this time, since the electric charge charged at the time of the rise of the PWM input remains in the capacitor C1, the voltage VC1 is expressed by the following equation (2).
[0041]
VC1 = CC1 × Tchg / C1 (2)
Here, Tchg is the charging time of the capacitor C1.
[0042]
Then, the voltage VC1 gradually decreases at a decrease rate CC1 / C1 from the value shown in the equation (2). The value of the voltage VG becomes substantially (VC1 + VD2 + Vbe7), and gradually decreases following the voltage VC1. Here, VD2 is a forward voltage of the diode D2, and Vbe7 is a forward voltage between the base and the emitter of the transistor Q7.
[0043]
Therefore, the rate of change of the load current IL also becomes a small value.
[0044]
Thereafter, at time T7, when the gate voltage VG becomes lower than the threshold voltage Vth, the source voltage VS becomes 0 volt, and the load current IL becomes zero amperes.
[0045]
The power supplied to the load 2 can be controlled by repeating the above-described operations from t1 to t7. Further, as can be understood from the change characteristic curve of the load current IL shown in FIG. 4F, it is possible to suppress an excessive current change that occurs at the time of rising and falling of the current by the PWM control.
[0046]
As described above, in the power control device 1 according to the first embodiment of the present invention, by providing the charging / discharging circuit 3, the buffer circuit 4, and the comparator 6, the gate voltage VG at the rising edge of the PWM input is sharply increased. Since the rise can be suppressed and the gate voltage VG can be prevented from sharply dropping when the PWM input falls, a sudden change in the load current due to the PWM control can be suppressed, and the generation of noise can be prevented. can do.
[0047]
Further, unlike the related art, the time required to reach the peak value at the time of the rise of the load current and the time required to reach the zero level at the time of the fall are not prolonged, so that the power loss can be reduced.
[0048]
Further, the charge current and discharge current of the charge / discharge circuit 3, the current Igsource flowing out of the buffer circuit 4, the current Igsink flowing therethrough, and the reference voltage Vref are used, and a total of five values are used to make the rising and falling currents of the load current IL. Since the rate of change can be controlled independently of each other, it is possible to optimally set a balance between the noise suppression effect and the power loss.
[0049]
Further, the Zener diode ZD1 can be omitted. In this case, the time from when the PWM signal becomes H level to when the load current IL starts to flow is delayed, but the noise suppression effect does not change.
[0050]
Furthermore, if the electronic switch FET1 is provided with a heating cutoff type additional function, and has a temperature detection circuit, a gate cutoff circuit, and a latch, the gate is turned off and energization is stopped before the MOS-FET is destroyed by heating. , Safety can be ensured.
[0051]
Next, a second embodiment of the power control device according to the present invention will be described. FIG. 5 is a schematic configuration diagram illustrating a power control device 11 according to the second embodiment, and FIG. 6 is a specific circuit configuration diagram.
As shown in FIG. 5, the power control device 11 includes a load 2, an electronic switch FET1 interposed between the battery and the load 2, and a first charging device, as in the first embodiment. A discharge circuit 3.
[0052]
A first buffer circuit 4 provided between the charge / discharge circuit 3 and the gate of the electronic switch FET1, a booster circuit 15 for boosting the battery voltage and outputting the voltage VP, and a gate voltage VG of the electronic switch FET1. And a predetermined reference voltage Vref, and a comparator 6 that outputs a signal indicating the result of the comparison to the charge / discharge circuit 3 via the Zener diode ZD1 and the capacitor C1.
[0053]
In the first embodiment, the number of the “charge / discharge circuit” and the number of the “buffer circuit” are respectively one. Therefore, they are simply referred to as the “charge / discharge circuit” and the “buffer circuit”. , Each of which has two “charge / discharge circuits” and “buffer circuits”. In order to distinguish between them, the first charge / discharge circuit 3 and the first buffer circuit 4 are used. The detailed circuit configuration is the same as that shown in FIG.
[0054]
Further, in the present embodiment, in addition to the above, a second charge / discharge circuit 13, a second buffer circuit 14, a capacitor C2, and a Zener diode ZD2 are provided. Further, a Zener diode ZD3 is provided between the gate and the source of the electronic switch FET1.
[0055]
Since the first charge / discharge circuit 3 and the first buffer circuit 4 shown in FIG. 6 are the same as those shown in FIG. 2, the same reference numerals are given and the description of the configuration is omitted.
[0056]
As shown in FIG. 6, the second charge / discharge circuit 13 has transistors Q21 to Q24, a current source CC2, and a resistor R10. Further, it is connected to the capacitor C2 and the Zener diode ZD2. A current mirror is formed by the transistors Q21 and Q22.
[0057]
The second buffer circuit 14 has a transistor Q25 serving as an emitter follower. The transistor Q25 buffers the output voltage VC2 of the second charge / discharge circuit 13, and outputs a voltage VC2-Vbe25 (Vbe25 is a voltage between the base and the emitter of the transistor Q25) to the first charge / discharge circuit 3. .
[0058]
FIG. 7 is a circuit diagram showing a detailed configuration of the booster circuit 15. As shown in FIG. 7, the booster circuit 15 includes an oscillator 17, diodes D30 and D31, capacitors C30 and C31, and a power supply VCC. , And boosts a high battery voltage of, for example, 42 volts to a desired voltage VP. The booster circuit 15 performs a charge pump operation using the oscillator 17, the diodes D30 and D31, and the capacitor C30. In this circuit, a value of VBATT + VCC-VD30-VD31 is obtained as the output voltage VP. Here, VD30 is a forward voltage of the diode D30, and VD31 is a forward voltage of the diode D31. The capacitor C31 is for smoothing the output voltage VP.
[0059]
Next, the operation of the power control device 11 according to the second embodiment will be described.
[0060]
Since the transistors Q21 and Q23 of the charge / discharge circuit 13 form a current mirror, the collector current of the transistor Q21 is equal to the current value of the current source CC1, and the collector current of the transistor Q22 is also equal to the current value of the current source CC1. Become.
[0061]
Then, when the slow start input to the second charge / discharge circuit 13 becomes H level, the transistor Q24 is turned on and the transistor Q23 is turned off, so that the capacitor C2 is charged by CC1 by the collector current of the transistor Q22. Thereby, the collector voltage VC2 of the transistor Q22 reaches a predetermined level.
[0062]
On the other hand, when the slow start input goes to L level, the transistor Q24 turns off and the transistor Q23 turns on, so that the electric charge accumulated in the capacitor C2 is discharged. As a result, voltage VC2 drops to zero volts. Here, the constant current is used only at the time of charging, but the constant current may be used at the time of discharging.
[0063]
Hereinafter, the operation at the time of slow start will be described with reference to the timing chart shown in FIG. In the figure, (a) is a slow start input signal, (b) is an output voltage VC2 of the second charge / discharge circuit 13, (c) is a PWM input, and (d) is an output voltage of the first charge / discharge circuit 3. VC1, (e) indicates the gate voltage VG of the electronic switch FET1, (f) indicates the source voltage VS of the electronic switch FET1, and (g) indicates the load current IL.
[0064]
When the slow start input is at the L level, as described above, the charge of the capacitor C2 is discharged, and the voltage VC2 is substantially zero volt. When the slow start input goes high at time t11, charging of the capacitor C2 is started. At this time, since the zener diode ZD2 is connected in series with the capacitor C2, as shown in FIG. 8B, the voltage VC2 once rises to the voltage Vzd2 (the voltage drop by the zener diode ZD2) and then becomes constant. The voltage rises to the voltage VP (the output voltage of the booster circuit 15) with a gradient. That is, the voltage VC2 is expressed by the following equation (3).
[0065]
VC2 = Vzd2 + CC2 × Tss / C1 (3)
Here, Tss is the elapsed time from when the slow start input becomes H level.
[0066]
Next, as shown in FIG. 3C, when a PWM input is given, the electronic switch FET1 is turned on in response to the PWM input pulse, and the load current IL flows. At this time, as shown in FIGS. 8D and 8E, the output voltage VC1 of the first charge / discharge circuit 3 and the gate voltage VG of the electronic switch FET1 also increase at the same gradient as the voltage VC2. become.
[0067]
Further, while the voltage VC2 is lower than VBATT (strictly, while VC2 is lower than VBATT + Vbe25 + VD1 + Vbe5 + Vth), the electronic switch FET1 performs a source follower operation, and the source voltage VS becomes VG-Vth. Here, Vth is an operation threshold voltage of the electronic switch FET1. For example, suppose that a bulb (load 2) rated at 12 volts is driven at a voltage VBATT = 36 volts. If Vzd2 = 16 volts, the voltage VS (source voltage) initially applied to the load is about 12 volts, so that the rush current can be suppressed to the same level as when the battery voltage VBATT is 12 volts.
[0068]
It is sufficient that the time until the voltage VC2 reaches the voltage VP is sufficient to match the time during which the rush current of the load 2 is generated. However, it is necessary to set a longer time so that the load 2 rises slowly. You can also.
[0069]
After the voltage VC2 exceeds the voltage VBATT, the source voltage VS settles to a constant value (VBATT-RDSon × IL). Here, RDSon is the ON resistance of the electronic switch FET1. If a slow start is not desired, the PWM signal may be driven in a state where the slow start input is set to the H level in advance.
[0070]
The operations of the first charging / discharging circuit 3 and the first buffer circuit 4 are the same as those of the first embodiment described above, and include the first charging circuit 3 and the first buffer circuit 4. Thus, it is possible to suppress the occurrence of noise at the time of rising and falling of the PWM input.
[0071]
In this manner, in the power control device 11 according to the second embodiment, the voltage can be gradually increased at the start of the voltage supply by providing the slow start input. Can be. Further, since the voltage applied to the load 2 can be set by the Zener diode ZD2, the load current IL can flow stably without being affected by the variation of the electronic switch FET1.
[0072]
Further, the initial voltage and voltage gradient of the slow start can be changed using the charge current of the second charge / discharge circuit 13, the value of the capacitor C2, and the value of the zener diode ZD2. Can be controlled.
[0073]
Further, the rise of the load current IL is determined by using a total of five values of the charging current and discharging current of the first charging / discharging circuit 3, the current Igsource flowing out of the first buffer circuit 4, the flowing current Igsink, and the reference voltage Vref. , And the falling current change rate can be controlled independently of each other, so that the balance between the noise suppression effect and the power loss can be optimally set.
[0074]
Further, similarly to the first embodiment, ZD1 can be omitted. In this case, the time required for the load current IL to flow after the PWM input signal becomes H level is delayed, but the noise suppression effect is not changed.
[0075]
Further, as shown in FIG. 9, it is also possible to set the PWM frequency and the duty ratio in the initial stage of lighting of the lamp (load 2) and both of them differently from those in the steady state. In this case, it is possible to finely adjust the lighting delay time.
[0076]
As described above, the vehicle power control device of the present invention has been described based on the illustrated embodiment. However, the present invention is not limited to this, and the configuration of each unit may be any configuration having the same function. Can be replaced.
[0077]
For example, in each of the above-described embodiments, a lamp load is taken as an example of the load 2, but the present invention is not limited to this, and can be applied to other loads such as a motor.
[0078]
Also, an example in which the electronic switch FET1 is interposed between the power supply and the load 2 has been described, but the present invention is not limited to this, and the electronic switch FET1 is provided between the load 2 and the ground. You can also.
[0079]
【The invention's effect】
As described above, according to the first and second aspects of the present invention, the first capacitor is charged at the leading edge (rising portion) of the PWM signal, so that the PWM signal gradually rises. Since the first capacitor is discharged at the trailing edge (falling portion) of the PWM signal, the PWM signal can fall slowly. Therefore, a sudden change in the load current can be suppressed, and the occurrence of noise can be reduced.
[0080]
According to the third aspect of the present invention, since the buffer circuit is provided between the first charge / discharge circuit and the electronic switch, it is possible to prevent a sudden change in the gate voltage of the electronic switch.
[0081]
According to the invention described in claim 4, when the gate voltage of the electronic switch is higher than the predetermined reference value, the charging and discharging of the first capacitor is stopped, so that after the gate voltage reaches the predetermined level, Since the voltage rises immediately, power loss can be reduced.
[0082]
According to the fifth aspect of the present invention, since the zener diode is connected to the first capacitor, the voltage can be immediately increased to a predetermined voltage level when the PWM signal rises.
[0083]
According to the present invention, when the slow start signal is given, the second capacitor is charged by the second charge / discharge circuit, so that the level of the PWM signal is gradually increased. Thus, it is possible to prevent a sudden change in the voltage when the PWM signal is input. Thereby, the load current can be stably supplied without being affected by the variation of the electronic switches.
[Brief description of the drawings]
FIG. 1 is a schematic configuration diagram illustrating a power control device according to a first embodiment of the present invention.
FIG. 2 is a circuit diagram showing a specific configuration of a power control device according to the first embodiment.
FIG. 3 is a circuit diagram illustrating a configuration of a booster circuit according to the first embodiment.
FIG. 4 is a timing chart showing an operation of the power control device according to the first embodiment.
FIG. 5 is a schematic configuration diagram illustrating a power control device according to a second embodiment of the present invention.
FIG. 6 is a circuit diagram showing a specific configuration of a power control device according to a second embodiment.
FIG. 7 is a circuit diagram illustrating a configuration of a booster circuit according to a second embodiment.
FIG. 8 is a timing chart showing the operation of the power control device according to the second embodiment.
FIG. 9 is an explanatory diagram showing an example in which a frequency and a duty ratio of a PWM input signal are different from those in a steady state according to the second embodiment.
FIG. 10 is a characteristic diagram showing a signal change according to a conventional power control device.
[Explanation of symbols]
1,11 Power control device
2 Load
3. Charge / discharge circuit, first charge / discharge circuit
4. Buffer circuit, first buffer circuit
5,15 booster circuit
6. Comparator (comparing means)
7,17 oscillator
13 Second charge / discharge circuit
14 Second buffer circuit
FET1 Electronic switch
C1 capacitor (first capacitor)
C2 capacitor (second capacitor)

Claims (7)

In a vehicle power control device that performs PWM control on a DC voltage output from a power supply to drive a load mounted on a vehicle,
An electronic switch that is interposed between the load and the power supply or between the load and the ground and switches on and off the power supply voltage,
A first capacitor for charging and discharging;
A first charge / discharge circuit that switches charging and discharging of the capacitor according to a PWM signal;
A terminal voltage of the first capacitor is supplied to the electronic switch to turn on and off the electronic switch.
The first charge / discharge circuit charges the first capacitor at a leading edge of the PWM signal and discharges the first capacitor at a trailing edge of the PWM signal. apparatus. The power control device for a vehicle according to claim 1, wherein the electronic switch is a field effect transistor, and applies a terminal voltage of the first capacitor to a gate of the field effect transistor. 3. The vehicle power control device according to claim 1, wherein a buffer circuit is provided between the first charge / discharge circuit and the electronic switch. Comparing means for comparing a gate voltage of the field effect transistor with a reference voltage,
One end of the first capacitor is connected to the output end of the first charge / discharge circuit, and the other end is connected to the output end of the comparing means;
When the comparing means determines that the gate voltage is higher than the reference voltage, the charging / discharging of the first capacitor is stopped, and when it is determined that the gate voltage is lower than the reference voltage, The power control device for a vehicle according to claim 2, wherein the first capacitor enables charging and discharging of the first capacitor. 5. The power control device for a vehicle according to claim 4, wherein a zener diode is interposed between an output terminal of the comparison unit and the first capacitor. A second capacitor and a second charge / discharge circuit are provided before the first charge / discharge circuit, and the second charge / discharge circuit is configured to receive the second capacitor when a slow start signal is input. The power supply apparatus for a vehicle according to any one of claims 1 to 5, wherein by charging the power supply, the output signal level is gradually increased to control the output signal level to reach a peak value. The power control device for a vehicle according to claim 6, wherein a Zener diode is disposed on a path for charging the second capacitor.

Images