JPH1131862A - Method of manufacturing semiconductor solid-state quantum structure - Google Patents
Method of manufacturing semiconductor solid-state quantum structureInfo
- Publication number
- JPH1131862A JPH1131862A JP18863497A JP18863497A JPH1131862A JP H1131862 A JPH1131862 A JP H1131862A JP 18863497 A JP18863497 A JP 18863497A JP 18863497 A JP18863497 A JP 18863497A JP H1131862 A JPH1131862 A JP H1131862A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- quantum structure
- dimensional quantum
- plane
- mixed crystal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 99
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 238000000034 method Methods 0.000 claims abstract description 32
- 239000013078 crystal Substances 0.000 claims abstract description 19
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 13
- 238000010030 laminating Methods 0.000 claims description 3
- 239000000758 substrate Substances 0.000 abstract description 14
- 229910000673 Indium arsenide Inorganic materials 0.000 abstract description 12
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 abstract description 12
- 239000007787 solid Substances 0.000 abstract 1
- 238000009826 distribution Methods 0.000 description 5
- 238000001312 dry etching Methods 0.000 description 3
- 238000010894 electron beam technology Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000001451 molecular beam epitaxy Methods 0.000 description 3
- 239000002096 quantum dot Substances 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 2
- 238000007687 exposure technique Methods 0.000 description 2
- 239000002994 raw material Substances 0.000 description 2
- 229910052786 argon Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000005284 excitation Effects 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 238000000171 gas-source molecular beam epitaxy Methods 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- 238000000103 photoluminescence spectrum Methods 0.000 description 1
Landscapes
- Semiconductor Lasers (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は、低閾値の半導体レ
ーザの活性層などに用いられる半導体立体量子構造の作
製方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for fabricating a semiconductor three-dimensional quantum structure used for an active layer of a low-threshold semiconductor laser.
【0002】[0002]
【従来の技術】従来より、高品質の半導体立体量子構造
の作製方法として、微細な島状構造が形成されるよう
に、格子常数の異なる半導体を積層する手法が多く用い
られている。例えば、GaAs層上に、GaAsと格子
常数の異なるInGaAsを成長させて立体量子構造を
作製する方法が、アプライド・フィジックス・レター
ズ、63巻、23号、1993年、3203−3205
頁(Applied Physics Letters, volume 63, No.23, 199
3 pp.3203-3205)に、ディ・レオナルドら(D. Leonard
et al.)によって報告されている。2. Description of the Related Art Conventionally, as a method for producing a high-quality semiconductor three-dimensional quantum structure, a method of laminating semiconductors having different lattice constants so as to form a fine island-like structure has been often used. For example, a method of growing a three-dimensional quantum structure by growing InGaAs having a lattice constant different from that of GaAs on a GaAs layer is disclosed in Applied Physics Letters, Vol. 63, No. 23, 1993, 3203-3205.
Page (Applied Physics Letters, volume 63, No.23, 199
3 pp.3203-3205) and D. Leonard et al.
et al.).
【0003】例えば、このような方法において、GaA
sの(100)面上にInGaAsを分子線エピタキシ
ー法によって成長させれば、直径30nm程度の量子ド
ット構造が1010cmー2程度以上の高密度で形成でき
る。For example, in such a method, GaAs
If InGaAs is grown on the (100) plane of s by molecular beam epitaxy, a quantum dot structure having a diameter of about 30 nm can be formed at a high density of about 10 10 cm −2 or more.
【0004】[0004]
【発明が解決しようとする課題】しかしながら、このよ
うな従来技術による自己形成的な半導体立体量子構造の
作製方法においては、以下の課題が存在する。However, the following problems exist in such a conventional method for fabricating a self-formed semiconductor three-dimensional quantum structure.
【0005】まず、平坦な基板の上に半導体立体量子構
造を作製する場合、半導体立体量子構造のサイズは通常
10〜20パーセント程度ばらつく。自己形成的な作製
手法を用いる場合、このばらつきは、半導体立体量子構
造の材料、成長条件、形成面の方位等によらずこの程度
の値となる。したがって、半導体立体量子構造からの発
光線幅については、本来期待されている狭線幅は実現で
きず、通常のバルク半導体からの発光線幅程度以上の広
がりとなってしまう。First, when fabricating a semiconductor three-dimensional quantum structure on a flat substrate, the size of the semiconductor three-dimensional quantum structure usually varies by about 10 to 20 percent. In the case of using a self-forming fabrication method, the variation has such a value regardless of the material of the semiconductor three-dimensional quantum structure, the growth conditions, the orientation of the formation surface, and the like. Therefore, as for the emission line width from the semiconductor three-dimensional quantum structure, the originally expected narrow line width cannot be realized, and the emission line width becomes wider than that of an ordinary bulk semiconductor.
【0006】また、基板に、エッチング等の手段で選択
的に半導体立体量子構造が形成され易い部分を作製し、
そこに半導体立体量子構造を選択的に形成する手法も存
在する。しかし、この手法においては、半導体立体量子
構造が形成される1つのパターンが半導体立体量子構造
の大きさの10倍程度の広い領域よりなるので、半導体
立体量子構造の密度が低下し、その結果十分な発光強度
を得ることも困難である。Further, a portion where a semiconductor three-dimensional quantum structure is easily formed selectively is formed on the substrate by means of etching or the like,
There is a technique for selectively forming a semiconductor three-dimensional quantum structure there. However, in this method, since one pattern in which the semiconductor three-dimensional quantum structure is formed has a wide area of about ten times the size of the semiconductor three-dimensional quantum structure, the density of the semiconductor three-dimensional quantum structure decreases, and as a result, It is also difficult to obtain a high emission intensity.
【0007】以上の理由から、従来技術においては、自
己形成的な半導体立体量子構造を、通常のバルク半導体
や量子井戸構造からの発光線幅以下の発光を実現できる
ほど良好な均一性を持つように作製することは困難であ
る。For the above reasons, in the prior art, the self-assembled three-dimensional semiconductor quantum structure has such a uniformity that the emission is smaller than the emission line width from the ordinary bulk semiconductor or quantum well structure. It is difficult to fabricate it.
【0008】本発明の目的は、このような従来技術の課
題を解決し、サイズや組成の均一性が良好で且つ密度も
十分な半導体立体量子構造を簡易に作製できる方法を提
供することにある。An object of the present invention is to solve the problems of the prior art and to provide a method for easily producing a semiconductor three-dimensional quantum structure having good uniformity in size and composition and sufficient density. .
【0009】[0009]
【課題を解決するための手段】本発明は、ある主面方位
上の第一の半導体層上に、格子常数の異なる第二の半導
体層を積層することによって、自己形成的に立体量子構
造を作製する方法において、立体量子構造の面内サイズ
より大きく且つ該面内サイズの5倍以下の大きさの領域
であって、領域間が該主面方位とは異なる面方位を有す
る面または面方位指数を有さない面により分断された、
該主面方位と同一の面方位を有する複数の領域を第一の
半導体層の表面に形成し、該複数の領域上に自己形成的
に立体量子構造を作製することを特徴とする半導体立体
量子構造の作製方法である。According to the present invention, a three-dimensional quantum structure is formed in a self-forming manner by laminating a second semiconductor layer having a different lattice constant on a first semiconductor layer on a certain principal plane orientation. In the manufacturing method, a region or a region having a plane orientation larger than the in-plane size of the three-dimensional quantum structure and not more than 5 times the in-plane size, and having a plane orientation different from the principal plane orientation between the regions. Divided by non-indexed surfaces,
Forming a plurality of regions having the same plane orientation as the principal plane direction on the surface of the first semiconductor layer, and forming a three-dimensional quantum structure in a self-forming manner on the plurality of regions; This is a method for manufacturing a structure.
【0010】本発明においては、半導体立体量子構造
を、平坦な基板上に製造するのではなく、異なる面方位
の面で分断された特定の大きさ(特定の面積)の領域を
含む表面凹凸構造を作製し、この複数の領域上に1つず
つ半導体立体量子構造を作製する。したがって、異なる
面方位の面上に供給された第二の半導体を構成する原子
は、その領域まで移動できず、その領域内上に供給され
た第二の半導体を構成する原子のみにより、非常に均一
なサイズの多数の半導体立体量子構造を作製できる。し
かも、この領域は適度に小さいので、半導体立体量子構
造の密度や発光強度の点でも問題は生じない。特に、多
数の各領域を同じ面積にしておけば、構造形成に使用さ
れる原子の総量も各領域の面積に比例して同じになるの
で、形状、サイズ、組成の均一性の高い多数の半導体立
体量子構造を製造できる。In the present invention, the semiconductor three-dimensional quantum structure is not manufactured on a flat substrate, but is formed on a surface uneven structure including a region of a specific size (specific area) divided by planes having different plane orientations. Are fabricated, and a semiconductor three-dimensional quantum structure is fabricated on each of the plurality of regions. Therefore, the atoms constituting the second semiconductor supplied on the planes having different plane orientations cannot move to the region, and are extremely affected only by the atoms constituting the second semiconductor supplied on the region. A large number of semiconductor three-dimensional quantum structures having a uniform size can be manufactured. In addition, since this region is appropriately small, there is no problem in terms of the density and the emission intensity of the semiconductor three-dimensional quantum structure. In particular, if a large number of regions have the same area, the total amount of atoms used for forming the structure also becomes the same in proportion to the area of each region, so that a large number of semiconductors with high uniformity in shape, size and composition A three-dimensional quantum structure can be manufactured.
【0011】[0011]
【発明の実施の形態】以下、本発明の好適な実施形態に
ついて説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below.
【0012】本発明において、立体量子構造を形成する
為の第一の半導体層上の領域の大きさは、立体量子構造
の面内サイズより大きく且つ面内サイズの5倍以下(面
積比)の範囲内で、適宜決定すれば良い。特に、立体量
子構造の面内サイズの2倍以上5倍以下(面積比)にす
ることが好ましい。同じ立体量子構造を多数製造するに
は、同じ面積の領域を多数形成すればよい。In the present invention, the size of the region on the first semiconductor layer for forming the three-dimensional quantum structure is larger than the in-plane size of the three-dimensional quantum structure and not more than five times the in-plane size (area ratio). What is necessary is just to determine suitably within a range. In particular, it is preferable to set the in-plane size of the three-dimensional quantum structure to twice to five times (area ratio). In order to manufacture many identical three-dimensional quantum structures, many regions having the same area may be formed.
【0013】この領域の形状は特に限定されず、例えば
後述する実施例1のように円形であってもよいし、また
例えば後述する実施例2のように一辺の長さが同じであ
る多角形(四角形等)であってもよい。この多角形(四
角形等)の場合、その多角形の領域は主面方位に対して
垂直な面により分断され、複数の多角形の領域同士は交
互に凹凸形状を構成する位置関係にすることができる。The shape of this region is not particularly limited, and may be, for example, a circle as in Example 1 described later, or a polygon having the same side length as in Example 2 described later. (Such as a square). In the case of this polygon (such as a quadrangle), the area of the polygon is divided by a plane perpendicular to the principal plane direction, and the areas of the plurality of polygons are alternately formed in a positional relationship forming an uneven shape. it can.
【0014】この領域の面方位は、第一の半導体層が形
成されている主面方位(成長主面)と同一であればよ
く、特に限定されない。ただし、通常自己形成的に半導
体立体量子構造を作製する際に用いられる(100)面
であることが好ましい。この領域の面方位が(100)
面であれば、一般に半導体立体量子構造の結晶成長の条
件が広くなる。The plane orientation of this region is not particularly limited as long as it is the same as the main plane orientation (growth main plane) on which the first semiconductor layer is formed. However, it is preferable that the (100) plane is usually used when a semiconductor three-dimensional quantum structure is produced in a self-forming manner. The plane orientation of this area is (100)
In the case of a plane, conditions for crystal growth of a semiconductor three-dimensional quantum structure are generally wide.
【0015】この複数の領域間を分断する面は、主面方
位(成長主面)とは異なる面方位を有する面、または面
方位指数を有さない面である。例えば後述する実施例1
のように曲面であってもよいし、また例えば後述する実
施例2のように主面方位に対して垂直な面であってもよ
い。The plane separating the plurality of regions is a plane having a plane orientation different from the principal plane orientation (growth principal plane) or a plane having no plane orientation index. For example, Example 1 described later
Or a surface perpendicular to the principal plane orientation, for example, as in Example 2 described later.
【0016】本発明において、第一の半導体および第二
の半導体に特に制限は無く、自己形成的に立体量子構造
を作製する為に従来より使用可能なことが知られた得る
各種の半導体を使用できる。特に、第一の半導体として
は、GaAsまたはGaAsに格子整合する三五族半導
体混晶、InPまたはInPに格子整合する三五族半導
体混晶が好ましく、第二の半導体としては、InxGa
1-xAs混晶(In組成比xは0より大きく1以下)、
InxGa1-xAs混晶(In組成比xは0.53より大
きく1以下)、InAsxP1-x混晶(As組成比xは0
より大きく1以下)が好ましい。In the present invention, the first semiconductor and the second semiconductor are not particularly limited, and various semiconductors which can be conventionally used for producing a three-dimensional quantum structure in a self-forming manner are used. it can. In particular, the first semiconductor is preferably GaAs or a Group III semiconductor mixed crystal lattice-matched to GaAs, InP or a Group III semiconductor mixed crystal lattice-matched to InP, and the second semiconductor is In x Ga
1-x As mixed crystal (In composition ratio x is more than 0 and 1 or less),
In x Ga 1-x As mixed crystal (In composition ratio x is larger than 0.53 and 1 or less), InAs x P 1-x mixed crystal (As composition ratio x is 0
Greater than 1).
【0017】ここで、第一の半導体がGaAsまたはG
aAsに格子整合する三五族半導体混晶である場合、良
好な半導体量子構造を実現する点から、第二の半導体は
In xGa1ーxAs混晶(In組成比xは0より大きく1
以下)であることが好ましい。また、第一の半導体がI
nPまたはInPに格子整合する三五族半導体混晶であ
る場合、第二の半導体はInAsxP1ーx混晶(As組成
比xは0より大きく1以下)であることが好ましい。Here, the first semiconductor is GaAs or G
In the case of a group III semiconductor mixed crystal lattice-matched to aAs,
In terms of realizing a good semiconductor quantum structure, the second semiconductor is
In xGa1-xAs mixed crystal (In composition ratio x is greater than 0 and 1
The following is preferred. The first semiconductor is I
Group III semiconductor mixed crystal lattice-matched to nP or InP
The second semiconductor is InAsxP1-xMixed crystal (As composition
The ratio x is preferably larger than 0 and equal to or smaller than 1).
【0018】[0018]
【実施例】以下、本発明の実施例について図面を参照し
て詳細に説明する。Embodiments of the present invention will be described below in detail with reference to the drawings.
【0019】<実施例1>図1は、実施例1の半導体立
体量子構造の作製方法の工程図である。Embodiment 1 FIG. 1 is a process chart of a method for fabricating a semiconductor three-dimensional quantum structure according to Embodiment 1.
【0020】まず、図1(a)に示すように、GaAs
基板10の(100)表面に、電子ビーム露光により直
径50nm程度の円形の多数の領域だけにレジスト11
が残るように露光した。ここで、円形領域のピッチは1
00nmとした。続いて、このレジスト11をマスクと
し、図1(b)に示すように、ドライエッチにより10
nm程度の厚さだけエッチングした。ここで、エッチさ
れた領域は、特定の面方位指数を有さない曲がった面で
ある。レジストを除去した後、分子線エピタキシー法を
用いて、図1(c)に示すように、この基板の表面上に
InAs12を0.5nm程度成長させて面内サイズ
(直径)約20nmの多数の半導体立体量子構造(In
As量子ドット)13を自己形成的に作製した。First, as shown in FIG.
On the (100) surface of the substrate 10, the resist 11 is applied only to a large number of circular regions having a diameter of about 50 nm by electron beam exposure.
Exposure was performed so as to remain. Here, the pitch of the circular area is 1
00 nm. Subsequently, using this resist 11 as a mask, as shown in FIG.
Etching was performed to a thickness of about nm. Here, the etched region is a curved surface having no specific plane orientation index. After removing the resist, as shown in FIG. 1C, InAs12 is grown to a thickness of about 0.5 nm on the surface of the substrate by molecular beam epitaxy to form a large number of in-plane sizes (diameters) of about 20 nm. Semiconductor three-dimensional quantum structure (In
As quantum dots) 13 were produced in a self-forming manner.
【0021】このように、平坦な(100)GaAs上
にInAsを成長すると、成長膜厚約0.5nmで、直
径20nm程度の半導体立体量子構造が自己形成的に成
長することが知られている。本実施例では、エッチされ
ずに残った直径50nmの平坦領域の上に、それぞれ一
つのInAs半導体立体量子構造が形成された。これ
は、平坦部以外の表面に付着した原子は段差部を越えて
移動することが困難なためである。また、非平坦部に付
着したInAsに関しては、表面領域に対して供給され
たInAsの量が半導体立体量子構造形成の臨界膜厚を
越さないため、半導体立体量子構造は形成されないため
である。As described above, when InAs is grown on flat (100) GaAs, it is known that a semiconductor three-dimensional quantum structure having a growth thickness of about 0.5 nm and a diameter of about 20 nm grows in a self-forming manner. . In this example, one InAs semiconductor three-dimensional quantum structure was formed on each of the flat regions having a diameter of 50 nm which were left unetched. This is because it is difficult for atoms attached to the surface other than the flat portion to move across the step. Further, as for InAs attached to the non-flat portion, the amount of InAs supplied to the surface region does not exceed the critical film thickness for forming the semiconductor three-dimensional quantum structure, so that the semiconductor three-dimensional quantum structure is not formed.
【0022】ここで、各平坦部に一つずつ形成された半
導体立体量子構造は、1つの構造を形成する原料となる
原子は、各平坦領域に供給される原子に他ならず、この
量は各領域の面積に比例するためほとんど一定であっ
た。したがって、各部の面積を精度良く同一にすること
によって同量の原子から半導体立体量子構造が形成され
るため、そのサイズは非常に均一なものとなった。Here, in the semiconductor three-dimensional quantum structure formed one by one in each flat portion, atoms serving as raw materials for forming one structure are not only atoms supplied to each flat region, and this amount is It was almost constant because it was proportional to the area of each region. Therefore, the semiconductor three-dimensional quantum structure is formed from the same amount of atoms by precisely equalizing the area of each part, and the size is very uniform.
【0023】図2は、本実施例によるInAs立体量子
構造の、面内サイズ分布を示すグラフである。このグラ
フに示すように、サイズの分布幅は約2パーセントと、
非常に小さくなっていた。FIG. 2 is a graph showing an in-plane size distribution of the InAs three-dimensional quantum structure according to the present embodiment. As shown in this graph, the size distribution width is about 2%,
It was very small.
【0024】<実施例2>図3は、実施例2の半導体立
体量子構造の作製方法の工程図である。<Embodiment 2> FIG. 3 is a process chart of a method for manufacturing a semiconductor three-dimensional quantum structure of Embodiment 2.
【0025】まず、図3(a)に示すように、GaAs
基板10の(100)表面に、電子ビーム露光によりレ
ジスト11に一辺50nmの市松模様のパターンを形成
した。しかる後、このパターンをマスクとし、図3
(b)に示すように、ドライエッチにより凸部と凹部の
間に5nm程度の段差をつけた。この段差部は、特定の
面方位指数を有さない。この基板を用い、分子線エピタ
キシー法を用いて表面の酸化膜を除去後、図3(c)に
示すように、表面上にInAs12を0.5nm程度成
長させて、面内サイズ約20nmの多数の半導体立体量
子構造(InAs量子ドット)13を自己形成的に作製
した。First, as shown in FIG.
On the (100) surface of the substrate 10, a checkerboard pattern of 50 nm on a side was formed on the resist 11 by electron beam exposure. Then, using this pattern as a mask, FIG.
As shown in (b), a step of about 5 nm was formed between the convex portion and the concave portion by dry etching. This step does not have a specific plane orientation index. After removing the oxide film on the surface of the substrate by molecular beam epitaxy using this substrate, as shown in FIG. 3C, InAs 12 is grown on the surface to a thickness of about 0.5 nm, and a large number of The semiconductor three-dimensional quantum structure (InAs quantum dot) 13 was self-formed.
【0026】本実施例では、各凸部、凹部に半導体立体
量子構造が1つずつ形成された。ここでも、1つの半導
体立体量子構造を形成する原料となる原子は、各領域ご
とに一定なため、非常に均一な半導体立体量子構造が実
現された。In this embodiment, one semiconductor three-dimensional quantum structure is formed in each of the projections and depressions. Also here, atoms as raw materials for forming one semiconductor three-dimensional quantum structure are constant in each region, so that a very uniform semiconductor three-dimensional quantum structure was realized.
【0027】<実施例3>実施例1、2において、Ga
As上に成長する半導体をIn0.5Ga0.5Asに変更し
たこと以外は、同様の工程を実施したところ、同様の良
好な効果が得られた。このような混晶系材料による半導
体立体量子構造では、各構造の間での組成の分布の制御
も必要であるが、本実施例によれば、同一量の原子から
1つの半導体立体量子構造が作製され、かつIn,Ga
ともに各領域への供給量はほとんど同一であるため、組
成も均一な構造が実現された。また、本実施例による構
造をGaAsで埋め込んだ構造の、アルゴンレーザを励
起源とした室温におけるフォトルミネッセンススペクト
ルを測定したところ、組成およびサイズの均一化によ
り、半値幅として約15meVという非常に良好な値が
得られた。<Embodiment 3> In Embodiments 1 and 2, Ga
Except that the semiconductor grown on As was changed to In 0.5 Ga 0.5 As, a similar process was performed, and the same favorable effect was obtained. In such a semiconductor three-dimensional quantum structure using a mixed crystal material, it is necessary to control the composition distribution between the structures. According to this embodiment, however, one semiconductor three-dimensional quantum structure is formed from the same amount of atoms. Fabricated, and In, Ga
In both cases, the supply amounts to the respective regions were almost the same, so that a structure having a uniform composition was realized. Further, when the photoluminescence spectrum at room temperature of the structure in which the structure according to the present embodiment was embedded with GaAs was measured using an argon laser as an excitation source, the composition and size were made uniform, and a very good half-width of about 15 meV was obtained. The value was obtained.
【0028】<実施例4>実施例2において、基板とし
てInPを用いたこと以外は、同様の工程を実施した。
ここで、表面としては(100)面を用い、また反応性
ドライエッチ技術によって、(100)面よりなる各平
坦部分の間を、(100)面に垂直な面とした。この表
面の上にガスソース分子線エピタキシーによって、In
Asを0.4nm成長させた。すると、実施例2と同様
に、各平坦部に一つずつInAsよりなる立体量子構造
が形成された。この構造は、実施例2の説明で用いた図
3(c)と同様であり、また半導体立体量子構造の面内
サイズのばらつきも、約2パーセントと非常に良好であ
った。Example 4 A similar process was performed as in Example 2, except that InP was used as the substrate.
Here, a (100) plane was used as a surface, and a plane perpendicular to the (100) plane was formed between the flat portions composed of the (100) plane by a reactive dry etching technique. On this surface, gas source molecular beam epitaxy
As was grown to 0.4 nm. Then, as in Example 2, a three-dimensional quantum structure made of InAs was formed on each flat portion. This structure is the same as that shown in FIG. 3C used in the description of the second embodiment, and the variation in the in-plane size of the semiconductor three-dimensional quantum structure was as good as about 2%.
【0029】以上の実施例1〜4では、GaAs基板、
またはInP基板上にパターンを形成し、その上に歪半
導体による立体量子構造を自己形成的に作製する工程に
ついて述べたが、本発明において使用する材料系は、こ
れらの基板上のものに限定されるものではなく、他のII
I V族半導体、またII VI族半導体等を用いても差し支
えない。In the first to fourth embodiments, the GaAs substrate,
Alternatively, the process of forming a pattern on an InP substrate and self-forming a three-dimensional quantum structure of a strained semiconductor thereon has been described, but the material system used in the present invention is limited to those on these substrates. Not the other II
An IV group semiconductor, a II VI group semiconductor, or the like may be used.
【0030】また、パターン形成方法についても、電子
ビーム露光技術、ドライエッチ技術によるものだけでな
く、他の露光技術、エッチング技術を用いてもよいし、
また結晶成長上現れる半導体表面上の特異な表面構造を
利用してもよい。The pattern forming method is not limited to the method using the electron beam exposure technique and the dry etching technique, but may use other exposure techniques and etching techniques.
Alternatively, a unique surface structure on the semiconductor surface that appears during crystal growth may be used.
【0031】[0031]
【発明の効果】以上説明したように、本発明の作製方法
によれば、サイズや組成の分布が非常に小さく、それら
の均一性が良好で、且つ密度も十分な半導体立体量子構
造を簡易に作製できる。特に、本発明により半導体立体
量子構造のサイズや組成等の均一性を向上すると、発光
線幅なども究極的に小さくすることが可能になるので、
本発明により作製した半導体立体量子構造は、理想的な
特性を有する半導体レーザの活性層(狭発光幅を利用す
る低閾値の半導体レーザの活性層)等として極めて有用
である。As described above, according to the manufacturing method of the present invention, it is possible to easily produce a semiconductor three-dimensional quantum structure having a very small size and composition distribution, good uniformity thereof, and sufficient density. Can be made. In particular, when the uniformity of the size and composition of the semiconductor three-dimensional quantum structure is improved by the present invention, the emission line width and the like can be ultimately reduced.
The semiconductor three-dimensional quantum structure manufactured according to the present invention is extremely useful as an active layer of a semiconductor laser having ideal characteristics (an active layer of a semiconductor laser with a low threshold utilizing a narrow emission width).
【図1】本発明の実施例1の工程図である。FIG. 1 is a process chart of Example 1 of the present invention.
【図2】実施例1において作製した半導体立体量子構造
の面内サイズの分布を示すグラフである。FIG. 2 is a graph showing an in-plane size distribution of a semiconductor three-dimensional quantum structure manufactured in Example 1.
【図3】本発明の実施例2の工程図である。FIG. 3 is a process chart of Example 2 of the present invention.
10 GaAs(100)基板 11 レジスト 12 InAs 13 InAsによる半導体立体量子構造 DESCRIPTION OF SYMBOLS 10 GaAs (100) substrate 11 Resist 12 InAs 13 Semiconductor three-dimensional quantum structure by InAs
Claims (8)
格子常数の異なる第二の半導体層を積層することによっ
て、自己形成的に立体量子構造を作製する方法におい
て、 立体量子構造の面内サイズより大きく且つ該面内サイズ
の5倍以下の大きさの領域であって、領域間が該主面方
位とは異なる面方位を有する面または面方位指数を有さ
ない面により分断された、該主面方位と同一の面方位を
有する複数の領域を第一の半導体層の表面に形成し、該
複数の領域上に自己形成的に立体量子構造を作製するこ
とを特徴とする半導体立体量子構造の作製方法。1. A method according to claim 1, wherein on a first semiconductor layer on a certain principal plane orientation,
In a method of self-forming a three-dimensional quantum structure by laminating second semiconductor layers having different lattice constants, a three-dimensional quantum structure having a size larger than the in-plane size of the three-dimensional quantum structure and not more than 5 times the in-plane size is provided. A plurality of regions having the same plane orientation as the main plane orientation, divided by a plane having a plane orientation different from the main plane orientation or a plane having no plane orientation index between the regions. A method for manufacturing a semiconductor three-dimensional quantum structure, comprising: forming a three-dimensional quantum structure on a surface of one semiconductor layer;
内サイズの2倍以上5倍以下である請求項1記載の半導
体立体量子構造の作製方法。2. The method for manufacturing a semiconductor three-dimensional quantum structure according to claim 1, wherein the size of the region is at least two times and at most five times the in-plane size of the three-dimensional quantum structure.
ある多角形である請求項1または2記載の半導体立体量
子構造の作製方法。3. The method for manufacturing a semiconductor three-dimensional quantum structure according to claim 1, wherein the shape of the region is a polygon having the same side length.
直な面により分断されており、複数の該多角形の領域同
士は交互に凹凸形状を構成する位置関係にある請求項3
記載の半導体立体量子構造の作製方法。4. The polygonal region is divided by a plane perpendicular to the main surface direction, and the plurality of polygonal regions are in a positional relationship of alternately forming a concavo-convex shape.
A manufacturing method of the semiconductor three-dimensional quantum structure according to the above.
項1〜4の何れか一項記載の半導体立体量子構造の作製
方法。5. The method according to claim 1, wherein the principal plane direction is a (100) plane.
に格子整合する三五族半導体混晶であり、第二の半導体
がInxGa1-xAs混晶で、In組成比xは0より大き
く1以下である請求項1〜5の何れか一項記載の半導体
立体量子構造の作製方法。6. The method according to claim 1, wherein the first semiconductor is GaAs or GaAs.
6. A mixed crystal of group III semiconductors lattice-matched to the following, wherein the second semiconductor is an In x Ga 1 -x As mixed crystal and an In composition ratio x is greater than 0 and 1 or less. 3. The method for producing a semiconductor three-dimensional quantum structure according to the above item.
子整合する三五族半導体混晶であり、第二の半導体がI
nxGa1-xAs混晶で、In組成比xは0.53より大
きく1以下である請求項1〜5の何れか一項記載の半導
体立体量子構造の作製方法。7. The first semiconductor is InP or a Group III semiconductor mixed crystal lattice-matched to InP, and the second semiconductor is IP.
n In x Ga 1-x As mixed crystal, a method for manufacturing a semiconductor steric quantum structure of any one of claims 1-5 In composition ratio x is less than 1 greater than 0.53.
子整合する三五族半導体混晶であり、第二の半導体がI
nAsxP1-x混晶で、As組成比xは0より大きく1以
下である請求項1〜5の何れか一項記載の半導体立体量
子構造の作製方法。8. The semiconductor according to claim 1, wherein the first semiconductor is InP or a Group III semiconductor mixed crystal lattice-matched to InP, and the second semiconductor is IP.
The method for producing a semiconductor three-dimensional quantum structure according to any one of claims 1 to 5, wherein the composition ratio x of As is greater than 0 and equal to or less than 1 in the nAs x P 1-x mixed crystal.
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5991535A (en) * | 1982-11-16 | 1984-05-26 | Matsushita Electric Ind Co Ltd | Setting switch of digital code |
WO2003069677A1 (en) * | 2002-02-12 | 2003-08-21 | Canon Kabushiki Kaisha | Structure, method of manufacturing the same, and device using the same |
US7387967B2 (en) | 2002-12-13 | 2008-06-17 | Canon Kabushiki Kaisha | Columnar structured material and method of manufacturing the same |
JP2014209609A (en) * | 2013-03-26 | 2014-11-06 | 京セラ株式会社 | Semiconductor laser |
-
1997
- 1997-07-14 JP JP18863497A patent/JP2993470B2/en not_active Expired - Fee Related
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5991535A (en) * | 1982-11-16 | 1984-05-26 | Matsushita Electric Ind Co Ltd | Setting switch of digital code |
WO2003069677A1 (en) * | 2002-02-12 | 2003-08-21 | Canon Kabushiki Kaisha | Structure, method of manufacturing the same, and device using the same |
US7282268B2 (en) | 2002-02-12 | 2007-10-16 | Canon Kabushiki Kaisha | Structure, method of manufacturing the same, and device using the same |
US7387967B2 (en) | 2002-12-13 | 2008-06-17 | Canon Kabushiki Kaisha | Columnar structured material and method of manufacturing the same |
US7892979B2 (en) | 2002-12-13 | 2011-02-22 | Canon Kabushiki Kaisha | Columnar structured material and method of manufacturing the same |
JP2014209609A (en) * | 2013-03-26 | 2014-11-06 | 京セラ株式会社 | Semiconductor laser |
Also Published As
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