JPS61222216A - Manufacture of superlattice semiconductor device - Google Patents
Manufacture of superlattice semiconductor deviceInfo
- Publication number
- JPS61222216A JPS61222216A JP6209085A JP6209085A JPS61222216A JP S61222216 A JPS61222216 A JP S61222216A JP 6209085 A JP6209085 A JP 6209085A JP 6209085 A JP6209085 A JP 6209085A JP S61222216 A JPS61222216 A JP S61222216A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- superlattice
- dimensional
- semiconductor layer
- superlattice semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02494—Structure
- H01L21/02496—Layer structure
- H01L21/02505—Layer structure consisting of more than two layers
- H01L21/02507—Alternating layers, e.g. superlattice
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02538—Group 13/15 materials
- H01L21/02546—Arsenides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
- H01L21/02639—Preparation of substrate for selective deposition
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Junction Field-Effect Transistors (AREA)
- Recrystallisation Techniques (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は超格子半導体の作製方法に係夛、特に二次元又
は三次元超格子半導体の作製方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a method for manufacturing a superlattice semiconductor, and particularly to a method for manufacturing a two-dimensional or three-dimensional superlattice semiconductor.
近年、半導体層を周期的に繰シ返し積層して。 In recent years, semiconductor layers have been repeatedly stacked periodically.
その量子効果により従来得られなかった電気的・光学的
特徴を有する超格子半導体素子の研究開発が盛んにな夛
つつある。前記超格子半導体素子を実現するには精密膜
厚制御技術、相互拡散の起こらない原子尺度で急峻な接
合界面を実現できる作製技術１組成の異なる材料の切り
換えが瞬時に行える作製技術等が要求されるが、超高真
空を用いた分子線エピタキシャル成長（ＭＢＥ ） 、
或いは有機金属ガスを用いた気相分解法（ＭＯＣＶＴ）
）等が実現°されたため２１層状に周動的な薄膜形成
が可能とまってきた。具体的な応用例としては１周期的
超格子４テンシャルを形成する事により、に空間のブリ
リアンゾーンにミニバンドを形成して負性抵抗素子を実
現しようというもの（ＵＳ Ｐａｔ＠ｎｔφ３．６２６
，２５７ Ｌｅｏ−Ｅｓａｋｉ ） 、量子井戸を設
ける事によシ半導体レーザーの発振波長を変化させよう
とするもの等がある。又前記超格子半導体素子によシ人
工的にエネルギーバンドの装飾をする事が現実となりつ
つある。例えば半導体レーザーは通常直接遷移屋半導体
であるＧａＡｓ等の化合物半導体で作製造れるが、単元
素半導体８１．Ｇ・或いは５ｉ−Ｇ・混晶の様な間接遷
移型半導体でも、超格子構造を用いそのに空間の伝導帯
構造を変化させれば、これら間接遷移型半導体を用いて
もレーザー発振ができる可能性がある。しかしながら１
以上の超格子半導体は一次元構造であり、二次元構造及
び三次元構造の超格子半導体は実現されていなかった。Due to the quantum effect, research and development of superlattice semiconductor devices that have electrical and optical characteristics not previously available are becoming more and more popular. In order to realize the superlattice semiconductor device, precise film thickness control technology, manufacturing technology that can realize a steep bonding interface on an atomic scale without interdiffusion, 1. Manufacturing technology that can instantly switch between materials with different compositions, etc. are required. However, molecular beam epitaxial growth (MBE) using ultra-high vacuum,
Or gas phase decomposition method using organometallic gas (MOCVT)
) etc., it has become possible to form a 21-layer thin film in a circumferential manner. A specific example of application is to create a negative resistance element by forming a mini-band in the brilliant zone of the space by forming a 1-periodic superlattice 4 tensile (US Pat@ntφ3.626).
, 257 Leo-Esaki), and others that attempt to change the oscillation wavelength of a semiconductor laser by providing a quantum well. Also, it is becoming a reality to artificially decorate energy bands in the superlattice semiconductor device. For example, a semiconductor laser is usually made of a compound semiconductor such as GaAs, which is a direct transition semiconductor, but a single element semiconductor 81. Even with indirect transition type semiconductors such as G or 5i-G mixed crystals, if the conduction band structure of the space is changed using a superlattice structure, it is possible to generate laser oscillation using these indirect transition type semiconductors. There is sex. However, 1
The above superlattice semiconductors have one-dimensional structures, and superlattice semiconductors with two-dimensional and three-dimensional structures have not been realized.
本発明の目的は上記従来技術の状況を鑑み、二次元又は
三次元構造をもつ超格子半導体の作製方法を提供し、−
次元超格子半導体よりも更に顕著な量子効果が期待でき
る二次元又は三次元超格子半導体を提供する事にある。In view of the above-mentioned state of the prior art, an object of the present invention is to provide a method for manufacturing a superlattice semiconductor having a two-dimensional or three-dimensional structure,
The object of the present invention is to provide a two-dimensional or three-dimensional superlattice semiconductor that can be expected to have a more significant quantum effect than a dimensional superlattice semiconductor.
上記の目的は二次元又は三次元超格子半導体を超微細加
工技術と選択エピタキシャル技術とを用いて作製した事
を特徴とする本発明の超格子半導体の作製方法によって
達成される。The above object is achieved by the method for producing a superlattice semiconductor of the present invention, which is characterized in that a two-dimensional or three-dimensional superlattice semiconductor is produced using an ultrafine processing technique and a selective epitaxial technique.
以下１本発明の実施例全図面を用いて詳細に説明する。 DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to all the drawings.
第１図は本発明の二次元の超格子半導体の作製方法を示
す斜視図であり 、 （、）は−次元超格子半導体の斜
視図であり、（ｂ）は超微細加工を行った一次元超格子
半導体の斜視図であり、（Ｃ）は（ｂ）の−次元超格子
半導体に選択エピタキシャル成長させて構成した二次元
超格子半導体の斜視図である。第１図（ａ） において
１は結晶基板であり１例えばＧａＡｓｅｓｔ、ｃ・等の
単結晶基板あるいは８１０□、 ８１．Ｎ４゜アモルフ
ァスＳｊ等の非単結晶基板等である。２は第１の半導体
層で１例えばＧａＡａ ＊ ５Ｌｚ−Ｇａ１−。FIG. 1 is a perspective view showing the method for manufacturing a two-dimensional superlattice semiconductor of the present invention, (,) is a perspective view of a -dimensional superlattice semiconductor, and (b) is a one-dimensional ultrafinely processed one-dimensional superlattice semiconductor. It is a perspective view of a superlattice semiconductor, and (C) is a perspective view of a two-dimensional superlattice semiconductor made to selectively epitaxially grow the -dimensional superlattice semiconductor of (b). In FIG. 1(a), reference numeral 1 denotes a crystal substrate, such as a single crystal substrate such as GaAsest, c., or 810□, 81. It is a non-single crystal substrate such as N4° amorphous Sj. 2 is the first semiconductor layer 1, for example GaAa*5Lz-Ga1-.
ＧａＡｓ ｅ ８１１−Ｇｅｌ −）Ｃｅ Ｐ型Ｓｉ
、 Ｇｏ等である。３は第２の半導体層で１例えばＧａ
ＡｔＡｓ 、 Ｎ型Ｓ１あるいはＧ・等である。GaAs e 811-Gel-)Ce P-type Si
, Go et al. 3 is the second semiconductor layer 1, for example Ga
AtAs, N-type S1 or G.
まず、 ＭＢＥ 、 ＭＯＣＶＤ等のエピタキシャル成
長装置を用いて、結晶基板１上に第１の半導体層をエピ
タキシャル成長させ、その上に第２の半導体層をエピタ
キシャル成長させる。この第１の半導体層と第２の半導
体層とを交互に繰シ返し任意の数の層だけ積層させる。First, using an epitaxial growth apparatus such as MBE or MOCVD, a first semiconductor layer is epitaxially grown on a crystal substrate 1, and a second semiconductor layer is epitaxially grown thereon. The first semiconductor layer and the second semiconductor layer are alternately and repeatedly stacked in an arbitrary number of layers.
次に作製した半導体層の表面にフォトレジストを塗付し
、レーザーのホログラフィを用いた線状或は、格子状の
マスクを用意し、それを介してＸ線露光或は直接描画可
能なイオンビーム、電子線リングラフィ等の超微細加工
技術を用いて、上記フォトレジストを露光する。Next, a photoresist is applied to the surface of the fabricated semiconductor layer, a linear or lattice mask is prepared using laser holography, and an ion beam that can be used for X-ray exposure or direct drawing is applied through the mask. The photoresist is exposed using ultrafine processing technology such as electron beam phosphorography.
レーザーを用いた場合、ホログラフィクリソグラフィに
よる周期（Ｐ、）はレーデ−波長（λ）の半分まで理論
的に可能である。When using lasers, holographic lithographic periods (P, ) of up to half the Lede wavelength (λ) are theoretically possible.
Ｐ＝−τ−
２ｓｕθ
θはレーザーの入射角である。例としてＡｒレーデ−を
用いた場合は１０００Ｘ〜２０００Ｘの周期の格子のマ
スクが作製可能である。電子線或いはイオン線の７オト
レジスト上の直接描画によれか、更に微細な１０００オ
ングストローム以下の格子をフォトレジスト上に形成す
ることができる。P=-τ-2suθ θ is the incident angle of the laser. For example, when an Ar radar is used, a mask with a grating having a period of 1000X to 2000X can be produced. Even finer gratings of 1000 angstroms or less can be formed on the photoresist by direct writing of electron beams or ion beams on the photoresist.
露光、現偉した格子状のフォトレジストをマスクとして
方向性の高いエツチング方法１例えば。For example, a highly directional etching method 1 using an exposed and exposed lattice-shaped photoresist as a mask.
四塩化炭素ガスを用いた反応性イオンエツチングによっ
て膜表面から基板界面まで溝を掘る。Grooves are dug from the film surface to the substrate interface by reactive ion etching using carbon tetrachloride gas.
第１図（ｂ）はエツチング終了後の一次元超格子半導体
の斜視図であシ、４はフォトレジストである。FIG. 1(b) is a perspective view of the one-dimensional superlattice semiconductor after etching, and 4 is a photoresist.
このフォトレジスト４を取シ去り、側面の付着物或いは
イオンによる損傷領域を除去した後ＭＢＥ 。After removing the photoresist 4 and removing deposits on the side surfaces or areas damaged by ions, MBE is performed.
ＭＯＣＶＤ等を用いて、その間げきにのみ所望の半導体
材料を選択的にエピタキシャル成長させる。第１図（ｅ
）において５は選択エピタキシャル成長させた第３の半
導体層である。第３の半導体層の構成材料は例えばＧａ
ＡｔＡｓ ＃ ８１ｚＧｅ１−１ ｘ ８１ 、 Ｇｏ
等である。A desired semiconductor material is selectively epitaxially grown only in those spaces using MOCVD or the like. Figure 1 (e
), 5 is a third semiconductor layer grown selectively epitaxially. The constituent material of the third semiconductor layer is, for example, Ga.
AtAs #81zGe1-1 x 81, Go
etc.
選択エピタキシャル成長に際しては、最終層である半導
体層３の上部表面を核成長の少ない或いは全く起こらな
い、例えば８１０２． Ｓｉ、Ｎ４層等で覆う必要があ
る。During selective epitaxial growth, the upper surface of the semiconductor layer 3, which is the final layer, is coated with a layer that causes little or no nucleation, for example 8102. It is necessary to cover it with a Si, N4 layer, etc.
又、堆積中にＨＣｌ等のエツチングガスを混入すること
も有効である。これらの層はフォトレジスト塗付の前段
階で被覆し、半導体層を格子状にエツチングする際同時
に除去し、溝以外の半導体層上部に残す。It is also effective to mix an etching gas such as HCl during deposition. These layers are applied prior to applying the photoresist and removed at the same time as the semiconductor layer is etched in a grid pattern, leaving them on top of the semiconductor layer except in the trenches.
以上、超微細加工技術と選択エピタキシャル成長を用ａ
た二次元超格子半導体について記載したが、同様にして
三次元超格子半導体を作製する事ができる。The above uses ultrafine processing technology and selective epitaxial growth.
Although a two-dimensional superlattice semiconductor has been described, a three-dimensional superlattice semiconductor can be produced in the same manner.
第２図は本発明の三次元の超格子半導体の作製方法を示
す斜視図であ！Ｄ 、 （１）は超微細加工を行った一
次元超格子半導体の斜視図であり、（ｂ）は（ａ）の−
次元超格子半導体に選択エピタキシャル成長させた三次
元超格子半導体の斜視図である。三次元超格子半導体の
作製方法は二次元超格子半導体の作製で法と同様である
ので、ここでは省略する。FIG. 2 is a perspective view showing the method for manufacturing a three-dimensional superlattice semiconductor of the present invention! D, (1) is a perspective view of a one-dimensional superlattice semiconductor subjected to ultrafine processing, and (b) is a - of (a).
FIG. 2 is a perspective view of a three-dimensional superlattice semiconductor grown selectively epitaxially on a three-dimensional superlattice semiconductor. The method for manufacturing a three-dimensional superlattice semiconductor is the same as the method for manufacturing a two-dimensional superlattice semiconductor, and therefore will not be described here.
この様に超微細加工技術と選択エピタキシャル成長を用
いた二次元超格子半導体又は三次元超格子半導体におい
ては、第３図に示すように、エネルギー状態密度Ｄ（Ｅ
）の分布は（１）の従来の一次元超格子半導体が階段状
の値をとるのに比して、（ｂ）の二次元超格子半導体は
周期的に離散的ｉ値を取り 、 （ｅ）の三次元超格子
半導体はさらにシャープな周期的な８関数列となる。こ
れらの周期的に離散的なエネルギー状態密度Ｄ（Ｅ）を
有する超格子半導体の光学的特性は吸収発光に際してよ
りシャーシなスペクトルとなり得る。In this way, in two-dimensional superlattice semiconductors or three-dimensional superlattice semiconductors using ultrafine processing technology and selective epitaxial growth, the energy state density D (E
) The distribution of (e ) is a three-dimensional superlattice semiconductor with an even sharper series of eight periodic functions. The optical properties of these superlattice semiconductors having a periodically discrete density of energy states D(E) can result in a more robust spectrum upon absorption and emission.
以上詳細に説明したように１本発明の超格子半導体の作
製方法によれば、二次元超格子半導体又は三次元超格子
半導体を簡易な作製方法で作製する事ができる。As explained in detail above, according to the method for manufacturing a superlattice semiconductor of the present invention, a two-dimensional superlattice semiconductor or a three-dimensional superlattice semiconductor can be manufactured by a simple manufacturing method.
第１図は本発明の二次元の超格子中°導体の作製方法を
示す斜視図であり、（ａ）は−次元超格子半導体の斜視
図であ−Ｄ 、 （ｂ）は超微細加工を行った一次元超
格子半導体の斜視図であり、（Ｃ）は（ｂ）の−次元超
格子半導体に選択エピタキシャル成長をさせて構成した
二次元超格子半導体の斜視図である。
第２図は本発明の三次元の超格子半導体の作製方法を示
す斜視図であり 、（ａｌは超微細加工を行りた一次元
超格子半導体の斜視図であり、（ｂ）は（＆）の−次元
超格子半導体に選択エピタキシャル成長させた三次元超
格子半導体の斜視図である。
第３図はエネルギー状態密度分布図を示し、それぞれ（
ａ）は従来の一次元超格子半導体、（ｂ）は三次元超格
子半導体、（ｃ）は三次元超格子半導体のエネルギー状
態密度分布図を示す。
１・・・結晶基板、２・・・第１の半導体層、３・・・
第２の半導体層、４・・・フォトレジスト、５・・・第
３の半導体層。 。FIG. 1 is a perspective view showing the method for manufacturing a two-dimensional superlattice medium conductor of the present invention, (a) is a perspective view of a -dimensional superlattice semiconductor, and (b) is a perspective view of a -D superlattice semiconductor. FIG. 10C is a perspective view of a one-dimensional superlattice semiconductor obtained by the above-mentioned method, and FIG. FIG. 2 is a perspective view showing the method for manufacturing a three-dimensional superlattice semiconductor of the present invention, (al is a perspective view of a one-dimensional superlattice semiconductor subjected to ultrafine processing, and (b) is a perspective view of a one-dimensional superlattice semiconductor that has undergone ultrafine processing. ) is a perspective view of a three-dimensional superlattice semiconductor selectively epitaxially grown on a -dimensional superlattice semiconductor of (
A) shows energy state density distribution diagrams of a conventional one-dimensional superlattice semiconductor, (b) a three-dimensional superlattice semiconductor, and (c) a three-dimensional superlattice semiconductor. DESCRIPTION OF SYMBOLS 1... Crystal substrate, 2... First semiconductor layer, 3...
2nd semiconductor layer, 4... photoresist, 5... third semiconductor layer. .
Claims (1)
エピタキシャル技術とを用いて作製した事を特徴とする
超格子半導体の作製方法。A method for producing a superlattice semiconductor, characterized in that a two-dimensional or three-dimensional superlattice semiconductor is produced using ultrafine processing technology and selective epitaxial technology.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6209085A JPS61222216A (en) | 1985-03-28 | 1985-03-28 | Manufacture of superlattice semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6209085A JPS61222216A (en) | 1985-03-28 | 1985-03-28 | Manufacture of superlattice semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61222216A true JPS61222216A (en) | 1986-10-02 |
Family
ID=13190006
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6209085A Pending JPS61222216A (en) | 1985-03-28 | 1985-03-28 | Manufacture of superlattice semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61222216A (en) |
Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01225175A (en) * | 1988-03-03 | 1989-09-08 | Nec Corp | field effect transistor |
| JPH0328831A (en) * | 1989-06-26 | 1991-02-07 | Matsushita Electric Ind Co Ltd | Nonlinear optical thin film |
| JPH03116822A (en) * | 1989-09-29 | 1991-05-17 | Natl Res Inst For Metals | How to form a quantum well box |
| JPH04125966A (en) * | 1990-09-17 | 1992-04-27 | Nec Corp | Semiconductor device and manufacture thereof |
| US5534444A (en) * | 1994-06-22 | 1996-07-09 | France Telecom | Process for producing an electrically controllable matrix of vertically structured quantum well components |
| US6780711B2 (en) | 1998-11-16 | 2004-08-24 | Matrix Semiconductor, Inc | Vertically stacked field programmable nonvolatile memory and method of fabrication |
| US6841813B2 (en) | 2001-08-13 | 2005-01-11 | Matrix Semiconductor, Inc. | TFT mask ROM and method for making same |
| US6843421B2 (en) | 2001-08-13 | 2005-01-18 | Matrix Semiconductor, Inc. | Molded memory module and method of making the module absent a substrate support |
| US6853049B2 (en) | 2002-03-13 | 2005-02-08 | Matrix Semiconductor, Inc. | Silicide-silicon oxide-semiconductor antifuse device and method of making |
| US6881994B2 (en) | 2000-08-14 | 2005-04-19 | Matrix Semiconductor, Inc. | Monolithic three dimensional array of charge storage devices containing a planarized surface |
| US6888750B2 (en) | 2000-04-28 | 2005-05-03 | Matrix Semiconductor, Inc. | Nonvolatile memory on SOI and compound semiconductor substrates and method of fabrication |
| US6897514B2 (en) | 2001-03-28 | 2005-05-24 | Matrix Semiconductor, Inc. | Two mask floating gate EEPROM and method of making |
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| US7005730B2 (en) | 2002-02-19 | 2006-02-28 | Matrix Semiconductor, Inc. | Memory module having interconnected and stacked integrated circuits |
| US7352199B2 (en) | 2001-02-20 | 2008-04-01 | Sandisk Corporation | Memory card with enhanced testability and methods of making and using the same |
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-
1985
- 1985-03-28 JP JP6209085A patent/JPS61222216A/en active Pending
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| JPH01225175A (en) * | 1988-03-03 | 1989-09-08 | Nec Corp | field effect transistor |
| JPH0328831A (en) * | 1989-06-26 | 1991-02-07 | Matsushita Electric Ind Co Ltd | Nonlinear optical thin film |
| JPH03116822A (en) * | 1989-09-29 | 1991-05-17 | Natl Res Inst For Metals | How to form a quantum well box |
| JPH04125966A (en) * | 1990-09-17 | 1992-04-27 | Nec Corp | Semiconductor device and manufacture thereof |
| US5534444A (en) * | 1994-06-22 | 1996-07-09 | France Telecom | Process for producing an electrically controllable matrix of vertically structured quantum well components |
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| US7615436B2 (en) | 2001-03-28 | 2009-11-10 | Sandisk 3D Llc | Two mask floating gate EEPROM and method of making |
| US7525137B2 (en) | 2001-08-13 | 2009-04-28 | Sandisk Corporation | TFT mask ROM and method for making same |
| US6843421B2 (en) | 2001-08-13 | 2005-01-18 | Matrix Semiconductor, Inc. | Molded memory module and method of making the module absent a substrate support |
| US6841813B2 (en) | 2001-08-13 | 2005-01-11 | Matrix Semiconductor, Inc. | TFT mask ROM and method for making same |
| US7250646B2 (en) | 2001-08-13 | 2007-07-31 | Sandisk 3D, Llc. | TFT mask ROM and method for making same |
| US7432599B2 (en) | 2002-02-19 | 2008-10-07 | Sandisk 3D Llc | Memory module having interconnected and stacked integrated circuits |
| US7005730B2 (en) | 2002-02-19 | 2006-02-28 | Matrix Semiconductor, Inc. | Memory module having interconnected and stacked integrated circuits |
| US7329565B2 (en) | 2002-03-13 | 2008-02-12 | Sanddisk 3D Llc | Silicide-silicon oxide-semiconductor antifuse device and method of making |
| US6853049B2 (en) | 2002-03-13 | 2005-02-08 | Matrix Semiconductor, Inc. | Silicide-silicon oxide-semiconductor antifuse device and method of making |
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| US9478495B1 (en) | 2015-10-26 | 2016-10-25 | Sandisk Technologies Llc | Three dimensional memory device containing aluminum source contact via structure and method of making thereof |
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