JPH11295697A - Driving method of liquid crystal display device and electronic equipment - Google Patents

Abstract

(57) [Object] To prevent the occurrence of disclination lines caused by the difference in polarity of the applied voltage between adjacent pixels. A frame period is divided into a plurality of fields, and the polarity of an applied voltage is inverted for each selection period while skipping several lines for each field.
The occurrence of disclination lines can be reduced by shortening the time during which the polarity of the voltage applied to each adjacent pixel is reversed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for driving a liquid crystal display, and more particularly to a method for driving an active matrix type liquid crystal display. Further, the present invention relates to a liquid crystal display device using a driving method of an active matrix liquid crystal display device, and an electronic apparatus including the liquid crystal display device.

[0002]

2. Description of the Related Art As a conventional driving method of an active matrix liquid crystal display device, there is a driving method as described in Japanese Patent Publication No. 29916/1993.

This driving method is a method of inverting the polarity of a voltage applied to each pixel for each scanning line as shown in FIG. 9A, or applying a voltage to each pixel as shown in FIG. 9B. This is a driving method in which the polarity of the voltage is reversed between adjacent devices. The main purpose of this driving method is to prevent flicker on the screen and to improve display unevenness.

[0004]

In the case of such a driving method, the voltages applied to adjacent pixels have opposite polarities during most of one frame period, as shown in FIG. If the polarities of the voltages applied to adjacent pixels are opposite, a disclination line is generated.

For example, in the configuration of the reflection type liquid crystal light valve shown in FIG. 7, reference numeral 71 denotes a polarizing means, 72 denotes a glass substrate, 73
Is a transparent electrode, 74 is an alignment film, 75 is a liquid crystal, 76 is an alignment film, 77 is a silicon substrate, and a circuit as shown in FIG. 6 is formed on the silicon substrate 77. A description will be given of an example of a liquid crystal mode in which a nematic liquid crystal having a negative rate anisotropy is inserted and the liquid crystal becomes dark when no voltage is applied to the liquid crystal.

An ON voltage is applied to each pixel to display white,
Disclination lines generated when the polarity of the voltage applied to adjacent pixels is opposite are darkened. FIG. 8 shows how the disclination line occurs. 81
-84 represent each pixel, and + and-represent the polarity of the voltage applied to each pixel. Reference numerals 85 to 88 denote the appearance of disclination lines occurring in each pixel. Thus, a dark disclination line is generated near the boundary between the pixels. The disclination line causes a decrease in image quality such as a decrease in contrast and a decrease in luminance.

[0007] As the definition of one pixel becomes smaller as the resolution becomes higher as in recent years, the ratio of the area where the disclination line occurs to the pixel area increases, and the deterioration of the image quality becomes more serious.

In particular, a light valve used for a liquid crystal projector or the like has a small screen size and is required to have high definition. Among them, in the case of a reflective liquid crystal light valve as disclosed in Japanese Patent Application Laid-Open No. 9-236814, the gap between each pixel is small and the pixel size is small, so that the influence of the disclination line is large and the image quality is also high. Will drop.

Further, in order to prevent disclination lines from being generated, it is possible to make the polarity of the voltage applied to all the pixels the same and to invert the polarity only for each frame, but flickering occurs.

[0010]

According to a first aspect of the present invention, in a liquid crystal display device of the active matrix type in which a switching element is provided for each pixel, a polarity of a voltage applied to each pixel on a first scanning line is provided. Is the same as the polarity of the voltage applied to each pixel on the scanning line adjacent to the first scanning line in one frame period, and is the same as the polarity of the first period in which the polarity is opposite to the potential of the common electrode. And a second period.

According to the above configuration, it is possible to reduce the occurrence of disclination lines that occur when the polarity of the voltage applied to adjacent pixels is opposite, and to improve the brightness and contrast of the liquid crystal display device. .

In the liquid crystal display device according to the present invention, the voltage applied to each pixel on the first scanning line is compared with the voltage applied to each pixel on the scanning lines on both sides of the first scanning line. It is characterized in that the sum of the first period is substantially the same for any scanning line.

According to the above configuration, it is possible to reduce the occurrence of disclination lines that occur when the polarity of the voltage applied to the adjacent pixels is opposite, and to improve the brightness and contrast of the liquid crystal display device. .

According to a third aspect of the present invention, one frame period is divided into N (N is an integer of 2 or more) sub-periods.
In each sub-period, the polarity of the applied voltage is inverted every scanning period while skipping every N scanning lines.

According to the above configuration, it is possible to reduce the occurrence of disclination lines that occur when the polarity of the voltage applied to the adjacent pixels is opposite, and to improve the brightness and contrast of the liquid crystal display device. .

In the liquid crystal display device according to the present invention, one frame period is divided into N (2 ≦ N ≦ 32 integers) sub-periods, and each sub-period is skipped for every N scanning lines and for each scanning period. The polarity of the applied voltage is inverted.

According to the above configuration, it is possible to reduce the occurrence of disclination lines which occur when the polarity of the voltage applied to the adjacent pixels is opposite, to improve the brightness and contrast of the liquid crystal display device, and to improve the control circuit. This has the effect that optimization can also be performed.

According to a fifth aspect of the present invention, in the liquid crystal display device, the order of the scanning lines to be scanned is changed for each of the sub-selection periods.

According to the above configuration, it is possible to reduce the occurrence of disclination lines that occur when the polarity of the voltage applied to the adjacent pixels is opposite, to improve the brightness and contrast of the liquid crystal display device, and to reduce flicker. It also has the effect of being able to.

According to a sixth aspect of the present invention, in the liquid crystal display device, the polarity of the voltage applied to each pixel on the same scanning line is the same.

According to the above configuration, it is possible to reduce the occurrence of disclination lines that occur when the polarity of the voltage applied to the adjacent pixels is opposite, and to improve the brightness and contrast of the liquid crystal display device. .

According to a seventh aspect of the present invention, in the liquid crystal display device, the polarity of the voltage applied to each pixel on the same scanning line is opposite for each pixel or every two pixels with respect to the potential of the common electrode. .

According to the above configuration, it is possible to reduce the occurrence of disclination lines which occur when the polarity of the voltage applied to adjacent pixels is opposite, to improve the brightness and contrast of the liquid crystal display device, and to reduce flicker. It also has the effect of being able to.

According to an eighth aspect of the invention, there is provided an electronic apparatus including a liquid crystal display device using the driving method according to the first to seventh aspects.

According to the above configuration, there is an effect that an electronic device which is bright, has high contrast, is easy to see, and has high display quality can be provided.

[0026]

Embodiments of the present invention will be described below with reference to the drawings.

The first to sixth embodiments are active matrices in which transistors are provided in respective pixels as shown in FIG. 6, and will be described with reference to the reflection type liquid crystal light valve shown in FIG.

In FIG. 6A, reference numeral 601 denotes an example of an equivalent circuit of a pixel portion. Reference numeral 602 denotes a transistor; 603, a gate of the transistor; 604, a source of the transistor;
605 is the drain of the transistor and the pixel electrode, 606
Denotes a liquid crystal, 607 denotes a storage capacitor, and 608 denotes a common electrode. (B) is a block diagram of an example of a drive circuit of the active matrix type liquid crystal display device.
11 is a signal line driver, 612 is a gate line driver, Y
1 to Yn indicate gate lines, and X1 to Xm indicate source lines.

Then, as shown in FIG.
The gate 603 of each pixel is connected to the gate line and the source 604 is connected to the source line.

FIG. 7 shows an example of the configuration of a reflection type liquid crystal light valve. Reference numeral 71 denotes a polarizing means, 72 denotes a glass substrate, 73 denotes a transparent electrode, 74 denotes an alignment film, 75 denotes a liquid crystal, and 75 denotes a liquid crystal.
Denotes an alignment film, 77 denotes a silicon substrate, and the silicon substrate 7
A circuit as shown in FIG. The liquid crystal 75 will be described as an example of a liquid crystal mode in which a nematic liquid crystal having a negative dielectric anisotropy is placed in a tilted vertical alignment cell, and becomes dark when no voltage is applied to the liquid crystal.

(Embodiment 1) FIG. 1 shows the timing at which a voltage is written to a pixel in each scanning line direction of the display shown in FIG. 5A and the polarity of the voltage. In the case where the polarities of the voltages applied to the pixels in the scanning line direction are the same, driving is performed in four fields, and Y1 to Yn in FIG.
(B) shows the timing when the transistor of each pixel on each of the gate lines Y1 to Yn is turned on and writing, and the state where the voltage is maintained with the same polarity after the writing is performed during one selection period. I have. The polarity of the voltage applied to each pixel is the same as the common electrode 608 in FIG.
Indicates the transparent electrode 73 of FIG. ) Are represented as positive and negative with respect to the potential V.

In FIG. 1, 1F is the first frame and 2F is the second frame.
Represents the frame.

In the first frame, first, in the first field indicated by 1f, gate lines Y1, Y5, Y9,.
Then, interlaced scanning is performed every four lines, selection is made, and writing is performed. (Gate lines corresponding to every eight lines from Y1) are written with positive polarity, and Y5,..., Yn-3 (gate lines corresponding to every eight lines from Y5) are written. Writing is performed with negative polarity. Gate line Y
The voltage on the positive polarity side is written into the pixel on one at the timing of a during one selection period at the timing of a, and is held until the timing of a 'of the second frame to be written next. Then, in the next selection period, the voltage on the negative polarity side is written to the pixel on the gate line Y5 at the timing of b during one selection period, and is held until the timing of b 'of the second frame to be written next. Then, in the next selection period, the voltage on the positive polarity side is written into the pixel on the gate line Y9 at the timing of c at the timing of c during one selection period, and is written and held until the timing of c 'of the second frame. . In this way, the polarity of the write voltage is inverted, and selection is sequentially performed by interlaced scanning every four lines, and the voltage on the negative polarity side is written to the gate line Yn-3 at the timing of d during one selection period. And hold until the timing of d ′ of the second frame to be written next. Thus, one field period (1f) ends, and the second field indicated by the next 2f starts.

In the second field, the gate lines Y2, Y
6, Y10,... Yn-2, interlaced scanning is performed every four lines, and a selection is made and writing is performed. Y2, Y1
0,... (Gate lines corresponding to every eight lines from Y2) are written with positive polarity, and Y6,.
, The gate lines corresponding to every eight lines) are written with negative polarity. The voltage on the positive polarity side is written to the pixel on the gate line Y2 during the one selection period at the timing of e, and is held until the timing of e 'of the second frame to be written next. Then, in the next selection period, the voltage on the negative polarity side is written into the pixel on the gate line Y6 at the timing of f during one selection period, and f ′ of the second frame to be written next is written.
Until the timing of. Then, in the next selection period, the voltage on the positive polarity side is written to the pixel on the gate line Y10 at the timing of g at the timing of g, and is held until the timing of g 'of the second frame to be written next. In this way, the polarity of the write voltage is inverted, and selection is sequentially performed by interlace scanning every four lines, and the voltage on the negative polarity side is written to the gate line Yn-2 during the one selection period at the timing of h. And holds until the timing of h 'of the second frame to be written next. This ends the two-field period, and the third field indicated by 3f starts.

In the third field, gate lines Y3, Y
7, Y11,..., Yn−1, interlaced scanning is performed every four lines, selection is made, and writing is performed. Y3, Y1
,... (Gate lines corresponding to every eight lines from Y3) are written with positive polarity, and Y7,.
, The gate lines corresponding to every eight lines) are written with negative polarity. The voltage on the positive polarity side is written into the pixel on the gate line Y3 at the timing of i during one selection period, and is held until the timing of i 'of the second frame to be written next. In the next selection period, the voltage on the negative polarity side is written to the pixel on the gate line Y7 at the timing of j during one selection period, and j ′ of the second frame to be written next is written.
Until the timing of. Then, in the next selection period, the voltage on the positive polarity side is written into the pixel on the gate line Y11 at a timing delayed by one selection period from j during one selection period, and from the j ′ of the second frame to be written next. It is held until the timing delayed for one selection period. In this way, the polarity of the write voltage is inverted, and selection is sequentially performed by interlaced scanning every four lines, and the voltage on the negative polarity side is written to the gate line Yn-1 for one selection period at the timing of k. And holds until the timing of k ′ of the second frame to be written next. This ends the three-field period, and the fourth field indicated by the next 4f is started.

In the fourth field, gate lines Y4, Y
8, Y12,..., Yn, interlaced scanning is performed every four lines, selection is made, and writing is performed. Y4, Y1
2,... (Gate lines corresponding to every 8 lines from Y4) are written with positive polarity, and Y8,..., Yn (gate lines corresponding to every 8 lines from Y8) are written with negative polarity. Is performed. The voltage on the positive polarity side is written into the pixel on the gate line Y4 at the timing of l during one selection period, and is held until the timing of l 'of the second frame to be written next. Then, in the next selection period, the voltage on the negative polarity side is written to the pixel on the gate line Y8 at the timing of m during one selection period, and is held until the timing of m 'of the second frame to be written next. Then, in the next selection period, the voltage on the positive polarity side is written into the pixel on the gate line Y12 at a timing delayed by one selection period from m, and the voltage on the positive side is written during the one selection period. The data is held until the timing delayed by one selection period. In this manner, the polarity of the write voltage is inverted, and selection is sequentially performed by interlaced scanning every four lines, and the voltage on the negative polarity side is written to the gate line Yn during one selection period at the timing of n. Is held until the timing of n 'of the second frame written to the second frame. This ends the four-field period, ends the first frame, and then starts the second frame.

In the second frame, a voltage is written to each pixel in the same manner as in the first frame, with a polarity opposite to that of the first frame. This operation is repeated, and each pixel is AC-driven.

By performing such driving, X1 to X1
The voltage applied to the source line indicated by Xm switches the polarity every selection period, for example, while the gate line Y2 shown in FIG.
For the applied voltage of each pixel above, the gate line Y1
As for the voltage applied to each of the above pixels, when looking at the first frame period in FIG. 1, only one field period (1f) in one frame period has the opposite polarity and the remaining period (2f to 2f).
4f) has the same polarity. The voltage applied to each pixel on the gate line Y3 below the voltage applied to each pixel on the gate line Y2 indicates the voltage applied to each pixel on the gate line Y2 in the first frame period in FIG. Almost only one field period (2f) has the opposite polarity and the remaining periods (1f and 3f to 4f)
f) has the same polarity.

Also, with respect to the voltage applied to each pixel on the gate line Y7 in FIG. 6B, the voltage applied to each pixel on the gate line Y6 above it is the first frame period in FIG. , Only one field period (from timing f to timing j) in one frame period has the opposite polarity and the same polarity during the remaining period (from timing 1f to timing f and timing j to termination of 4f). become. And
The voltage applied to each pixel on the gate line Y8 thereunder is substantially only for one field period (from timing j to timing m) in one frame period in the first frame period in FIG. The remaining period (1f
From the timing of j to the timing of m and the end of 4f) have the same polarity. Therefore, the total of the periods of the opposite polarities on the scanning lines on both sides adjacent to any scanning line is two field periods (one field period on each of the upper and lower sides).
Is almost equal to (However, in one field period 1f at the beginning of each frame period, for a gate line whose polarity is switched by interlaced scanning, writing is performed from the start of one field period 1f to the immediately preceding gate line. Or the difference between the period from the start of one field period 1f to the timing at which writing is performed and the period from the start of one field period 1f one selection period before to the timing at which writing is performed, As described above, the voltage applied to each pixel on each gate line is opposite to the voltage applied to the adjacent upper and lower pixels for only about one field period in one frame period. Since the polarity can be the same for the rest of the period, the occurrence of disclination lines can be reduced. , Improved contrast,
Brightness can be improved, and image quality can be greatly improved.

In the above embodiment, a method of applying a voltage to each pixel as shown in FIG. 5A has been described.
The polarity is inverted for each source line as shown in FIG.
Even if the polarity is inverted every two source lines as shown in FIG.

The diagram shown in FIG. 1 shows the polarity of the voltage applied to each pixel, but does not show the voltage level actually applied. As the voltage actually applied to each pixel, voltages having different voltage levels are applied in accordance with display data.

(Embodiment 2) This embodiment is a driving method in the case where the number of field periods divided into one frame period is changed to eight field periods by the same driving method as in the first embodiment.

FIG. 2 shows the timing at which a voltage is written to a pixel in each scanning line direction of the display shown in FIG. 5A and the polarity of the voltage. In the case where the polarity of the voltage applied to the pixels in the scanning line direction is the same, driving is performed in eight fields, and Y1 to Yn in FIG. 2 are Y1 to Yn in FIG.
3 shows the timing when the transistor of each pixel on each gate line is turned on and writing is performed, and the state where the voltage is maintained with the same polarity after the writing is performed during one selection period. The polarity of the voltage applied to each pixel is shown in FIG.
(The common electrode 608 is the transparent electrode 7 shown in FIG. 7).
3 is shown. ) Are represented as positive and negative with respect to the potential V.

In FIG. 2, 1F is the first frame and 2F is the second frame.
Represents the frame.

In the first frame, first, gate lines Y1, Y9,..., Yn-7 and 8 in a first field indicated by 1f.
Interlaced scanning is performed for each line, a selection is made, and writing is performed. Y1, Y17,..., Yn-7 (from Y1 to 1
Writing is performed with a positive polarity on the gate lines corresponding to every six lines), and writing is performed with a negative polarity on the Y9, Y25,... (Gate lines corresponding to every 16 lines from Y9).
The voltage on the positive polarity side is written into the pixel on the gate line Y1 during the one selection period at the timing of a, and is held until the timing of a 'of the second frame to be written next. Then, in the next selection period, the voltage on the negative polarity side is written into the pixel on the gate line Y9 at the timing of b during one selection period, and is held until the timing of b 'of the second frame to be written next. As described above, the polarity of the write voltage is inverted, and the polarity is sequentially selected by interlaced scanning for every eight lines, and the voltage is written to each pixel on the gate line Yn-7 and held until the next write. This ends one field period, and the second field indicated by the next 2f is started.

In the second field, the gate lines Y2, Y1
.., Yn-6 and interlaced scanning for every eight lines are performed, selection is made, and writing is performed. Y2, Y18, ...
.., Yn-6 (gate line corresponding to every 16 lines from Y2)
Are written with positive polarity, and Y10, Y26,...
(Gate lines corresponding to every 16 lines from Y10) are written with negative polarity. The voltage on the positive polarity side is written into the pixel on the gate line Y2 at a timing of c during one selection period, and is held until the timing of c 'of the second frame to be written next. Then, in the next selection period, the voltage on the negative polarity side is written into the pixel on the gate line Y10 at the timing of d during one selection period, and is held until the timing of d 'of the second frame to be written next. in this way,
While inverting the polarity of the write voltage, selection is sequentially performed by interlaced scanning every eight lines, and the voltage is written to each pixel on the gate line Yn-6 and held until the next write. This ends the two-field period, and the third field indicated by the next 3f is started.

As described above, in the third field, interlaced scanning is performed for every eight lines with the gate lines Y3, Y11,..., Yn-5, and selection is made, and writing is performed. Y
, Y19,..., Yn-5 (gate lines corresponding to every 16 lines from Y3) are written with positive polarity, and Y1
1, Y27,... (Gate lines corresponding to every 16 lines from Y11) are written with negative polarity. Gate line Y
The voltage on the positive polarity side is written into the upper pixel 3 during one selection period at the timing of e, and is held until the timing of e 'of the second frame to be written next. Then, a gate line is selected by interlaced scanning every eight lines, and a voltage is written to each pixel on the selected gate line while switching the polarity of the voltage applied to each pixel for each selection period, and then written to the next pixel. Hold up to

In the fourth field, the gate lines Y4, Y1
2,..., Yn-4 and interlaced scanning for every 8 lines are performed, selection is made, and writing is performed. Y4, Y20, ...
·, Yn-4 (gate line corresponding to every 16 lines from Y4)
Are written with positive polarity, and Y12, Y28,.
(Gate lines corresponding to every 16 lines from Y12) are written with negative polarity. The voltage on the positive polarity side is written into the pixel on the gate line Y4 at the timing of f during one selection period, and is held until the timing of f 'of the second frame to be written next. Then, a gate line is selected by interlaced scanning every eight lines, and a voltage is written to each pixel on the selected gate line while switching the polarity of the voltage applied to each pixel for each selection period, and then written to the next pixel. Hold up to

In the fifth field, the gate lines Y5, Y1
3,..., Yn−3 and interlaced scanning for every eight lines are performed, selection is made, and writing is performed. Y5, Y21, ...
·, Yn-3 (gate line corresponding to every 16 lines from Y5)
Are written with positive polarity, and Y13, Y29,.
(Gate lines corresponding to every 16 lines from Y13) are written with negative polarity. The voltage on the positive polarity side is written to the pixel on the gate line Y5 at the timing of g during one selection period, and is held until the timing of g 'of the second frame to be written next. Then, a gate line is selected by interlaced scanning every eight lines, and a voltage is written to each pixel on the selected gate line while switching the polarity of the voltage applied to each pixel for each selection period, and then written to the next pixel. Hold up to

In the sixth field, the gate lines Y6, Y1
4,..., Yn-2 and interlaced scanning for every eight lines are performed, and selection is made and writing is performed. Y6, Y22, ...
.., Yn-2 (gate line corresponding to every 16 lines from Y6)
Are written with positive polarity, and Y14, Y30,...
(Gate lines corresponding to every 16 lines from Y14) are written with negative polarity. The voltage on the positive polarity side is written into the pixel on the gate line Y6 at the timing of h during one selection period, and is held until the timing of h 'of the second frame to be written next. Then, a gate line is selected by interlaced scanning every eight lines, and a voltage is written to each pixel on the selected gate line while switching the polarity of the voltage applied to each pixel for each selection period, and then written to the next pixel. Hold up to

In the seventh field, the gate lines Y7, Y1
5,..., Yn-1 and interlaced scanning for every 8 lines are performed, selection is made, and writing is performed. Y7, Y23, ...
.., Yn-1 (gate line corresponding to every 16 lines from Y7)
Are written with positive polarity, and Y15, Y31,...
(Gate lines corresponding to every 16 lines from Y15) are written with negative polarity. The voltage on the positive polarity side is written to the pixel on the gate line Y7 at the timing of i during one selection period, and is held until the timing of i 'of the second frame to be written next. Then, a gate line is selected by interlaced scanning every eight lines, and a voltage is written to each pixel on the selected gate line while switching the polarity of the voltage applied to each pixel for each selection period, and then written to the next pixel. Hold up to

In the eighth field, the gate lines Y8, Y1
6,..., Yn and interlaced scanning for every 8 lines are performed, and selection is made and writing is performed. Y8, Y24, ...,
Yn (gate line corresponding to every 16 lines from Y8) is written with positive polarity, and Y16, Y32,.
A gate line corresponding to every 16 to 16 lines) is written with negative polarity. The voltage on the positive polarity side is written to the pixel on the gate line Y8 at the timing of j during one selection period, and is held until the timing of j ′ of the second frame to be written next. Then, a gate line is selected by interlaced scanning every eight lines, and a voltage is written to each pixel on the selected gate line while switching the polarity of the voltage applied to each pixel for each selection period, and then written to the next pixel. Hold up to

Thus, the first frame ends after the eighth field is completed, and then the second frame is started.

In the second frame, a voltage is written to each pixel in the same manner as in the first frame with a polarity opposite to that of the first frame. This operation is repeated, and each pixel is AC-driven.

By performing such driving, X1 to X1
The voltage applied to the source line indicated by Xm switches the polarity every selection period, for example, while the gate line Y shown in FIG.
2 with respect to the applied voltage of each pixel on the gate line Y
As for the voltage applied to each pixel on 1 in the first frame period of FIG. 2, almost one field period (1f) in one frame period has the opposite polarity and the remaining period (2f).
8f) have the same polarity. Then, with respect to the voltage applied to each pixel on the gate line Y2, the voltage applied to each pixel on the gate line Y3 below the same applies to the first frame period in FIG. Almost only one field period (2f) has the opposite polarity and the remaining periods (1f and 3f ...
8f) has the same polarity.

The voltage applied to each pixel on the gate line Y6 on the gate line Y7 in FIG. 6B is different from the voltage applied to each pixel on the gate line Y6 in the first frame period in FIG. , Only one field period (6f) in one frame period has the opposite polarity and the remaining periods (1f to 5f and 7f)
f-8f) have the same polarity. Then, with respect to the voltage applied to each pixel on the gate line Y7, the voltage applied to each pixel on the gate line Y8 below the voltage applied to each pixel on the gate line Y7 in the first frame period in FIG. Almost only one field period (7f) has the opposite polarity and the remaining period (1f to 6f)
And 8f) have the same polarity. Accordingly, the total of the periods of the opposite polarity in the adjacent scanning lines for any scanning line is substantially equal to the two-field period (one field period in each of the upper and lower sides). (However, in one field period 1f at the beginning of each frame period, for a gate line whose polarity is switched by interlaced scanning, writing is performed from the start of one field period 1f to the immediately preceding gate line. Or the difference between the period from the start of one field period 1f to the timing at which writing is performed and the period from the start of one field period 1f one selection period before to the timing at which writing is performed, As described above, the voltage applied to each pixel on each gate line is opposite to the voltage applied to the adjacent upper and lower pixels for only about one field period in one frame period. Since the polarity can be the same for the rest of the period, the occurrence of disclination lines can be reduced. , Improved contrast,
Brightness can be improved, and image quality can be greatly improved.

In the above embodiment, the method of applying a voltage to each pixel as shown in FIG. 5A has been described.
The polarity is inverted for each source line as shown in FIG.
Even if the polarity is inverted every two source lines as shown in FIG. (FIG. 5 shows Example 1
As shown in (1), the polarity is inverted every four pixels in the gate line direction in order to show a case where one frame period is divided into four fields for driving. In the second embodiment, the polarity is inverted every eight pixels. change. Further, the diagram shown in FIG. 2 shows the polarity of the voltage applied to each pixel as in FIG. 1 used in the description of the first embodiment, and does not show the voltage level actually applied. As the voltage actually applied to each pixel, voltages having different voltage levels are applied in accordance with display data.

(Embodiment 3) FIG. 3 shows a diagram relating to Embodiment 3 in FIG.

FIG. 3 shows the polarity of the voltage applied to each pixel similarly to FIGS. 1 and 2 used in the description of the first and second embodiments, and does not show the voltage level actually applied. Absent. As the voltage actually applied to each pixel, voltages having different voltage levels are applied in accordance with display data. The polarity of the voltage applied to each pixel is expressed as positive or negative with reference to the potential V of the common electrode 608 in FIG. 6 (the common electrode 608 indicates the transparent electrode 73 in FIG. 7).

In FIG. 3, 1F is the first frame and 2F is the second frame.
Represents the frame.

In the first frame, the gate lines Y1, Y5, Y9,...
Then, interlaced scanning is performed every four lines, selection is made, and writing is performed. (Gate lines corresponding to every eight lines from Y1) are written with positive polarity, and Y5,..., Yn-3 (gate lines corresponding to every eight lines from Y5) are written. Writing is performed with negative polarity. Gate line Y
The voltage on the positive polarity side is written into the pixel on one at the timing of a during one selection period at the timing of a, and is held until the timing of a 'of the second frame to be written next. Then, in the next selection period, the voltage on the negative polarity side is written to the pixel on the gate line Y5 at the timing of b during one selection period, and is held until the timing of b 'of the second frame to be written next. Then, in the next selection period, the voltage on the positive polarity side is written to the pixel on the gate line Y9 at the timing of c at the timing of c for one selection period, and is held until the timing of c 'of the second frame to be written next. In this way, the polarity of the write voltage is inverted, and selection is sequentially performed by interlaced scanning every four lines, and the voltage on the negative polarity side is written to the gate line Yn-3 during one selection period at the timing of d. It is held until the timing of d 'of the second frame to be written next.
This ends one field period, and the second field indicated by the next 2f is started.

In the second field, the gate lines Y3, Y
7, Y11,..., Yn−1, interlaced scanning is performed every four lines, selection is made, and writing is performed. Y3, Y1
,... (Gate lines corresponding to every eight lines from Y3) are written with positive polarity, and Y7,.
, The gate lines corresponding to every eight lines) are written with negative polarity. The voltage on the positive polarity side is written into the pixel on the gate line Y3 during the one selection period at the timing of e, and is held until the timing of e 'of the second frame to be written next. Then, in the next selection period, the voltage on the negative polarity side is written into the pixel on the gate line Y7 at the timing of f during one selection period, and f ′ of the second frame to be written next is written.
Until the timing of. Then, in the next selection period, the voltage on the positive polarity side is written into the pixel on the gate line Y11 at a timing delayed by one selection period from f, and the voltage on the positive polarity side is written during the one selection period from f ′ of the second frame written next. The data is held until the timing delayed by one selection period. In this way, selection is performed sequentially while inverting the polarity of the write voltage every four lines, and the voltage on the negative polarity side is written to the gate line Yn-1 for one selection period at the timing of g, and then is written. Hold until the timing of g ′ of the second frame to be performed. This ends the two-field period, and the third field indicated by the next 3f is started.

In the third field, the gate lines Y2, Y
6, Y10,... Yn-2, interlaced scanning is performed every four lines, and a selection is made and writing is performed. Y2, Y1
0,... (Gate lines corresponding to every eight lines from Y2) are written with positive polarity, and Y6,.
, The gate lines corresponding to every eight lines) are written with negative polarity. The voltage on the positive polarity side is written into the pixels on the gate line Y2 during the one selection period at the timing of h, and is held until the timing of h 'of the second frame to be written next. In the next selection period, the voltage on the negative polarity side is written to the pixel on the gate line Y6 at the timing of i during one selection period, and i ′ of the second frame to be written next is written.
Until the timing of. Then, in the next selection period, the voltage on the positive polarity side is written into the pixel on the gate line Y10 at the timing of j at the timing of j, and is held until the timing of j 'of the second frame to be written next. As described above, while the polarity of the write voltage is inverted, the selection is sequentially performed by the interlaced scanning every four lines, and the gate line Yn-2 is selected.
The voltage on the negative polarity side is written at the timing of k during one selection period, and is held until the timing of k 'of the second frame to be written next. This ends the three-field period, and the fourth field indicated by the next 4f is started.

In the fourth field, the gate lines Y4, Y
8, Y12,..., Yn, interlaced scanning is performed every four lines, selection is made, and writing is performed. Y4, Y1
2,... (Gate lines corresponding to every 8 lines from Y4) are written with positive polarity, and Y8,..., Yn (gate lines corresponding to every 8 lines from Y8) are written with negative polarity. Is performed. The voltage on the positive polarity side is written into the pixel on the gate line Y4 at the timing of l during one selection period, and is held until the timing of l 'of the second frame to be written next. Then, in the next selection period, the voltage on the negative polarity side is written to the pixel on the gate line Y8 at the timing of m during one selection period, and is held until the timing of m 'of the second frame to be written next. Then, in the next selection period, the voltage on the positive polarity side is written into the pixel on the gate line Y12 at a timing delayed by one selection period from m, and the voltage on the positive side is written during the one selection period. The data is held until the timing delayed by one selection period. In this way, the polarity of the writing voltage is inverted, and selection is sequentially performed by interlaced scanning every four lines, and the voltage on the negative polarity side is written to the gate line Yn at a timing of n during one selection period. It is held until the timing of n 'of the second frame to be written. This ends the four-field period, ends the first frame, and then starts the second frame.

In the second frame, a voltage is written to each pixel in the same manner as in the first frame, with a polarity opposite to that of the first frame. This operation is repeated, and each pixel is AC-driven.

By performing such driving, X1 to X1
The voltage applied to the source line indicated by Xm switches the polarity every selection period, for example, while the gate line Y shown in FIG.
2 with respect to the applied voltage of each pixel on the gate line Y
As for the voltage applied to each pixel on 1 in the first frame period of FIG. 3, almost two field periods (1f to 2f) in one frame period have opposite polarities and the remaining periods (3f to 4f). ) Have the same polarity. Then, the gate line Y2
For the applied voltage of each pixel above, the gate line Y3 below it
As for the voltage applied to each of the above pixels, when looking at the first frame period in FIG. 3, almost one field period (2f) in one frame period has the opposite polarity and the remaining periods (1f and 3f to 4f). Have the same polarity.

Further, with respect to the voltage applied to each pixel on the gate line Y7 in FIG. 6B, the voltage applied to each pixel on the gate line Y6 above it is the first frame period in FIG. , Only one field period (from timing f to timing i) in one frame period has the opposite polarity and the same polarity during the remaining period (from timing 1f to i and timing from i to the end of 4f). become. Then, the voltage applied to each pixel on the gate line Y8 thereunder is substantially two field periods in one frame period (m from the timing of f in the first frame period in FIG. 3).
) Only the reverse polarity and the remaining period (1f ~
(From the timing of f and the timing of m to the end of 4f)
Have the same polarity. Therefore, the total of the periods of the opposite polarity in the scanning lines on both sides adjacent to any one of the scanning lines is substantially equal to the three-field period (the two-field period on the upper side and the one-field period on the lower side). (However, in one field period 1f at the beginning of each frame period, the gate line whose polarity is switched by interlaced scanning is selected.
For the immediately preceding gate line, the period from the start of one field period 1f to the timing at which writing is performed, or the period from the start of one field period 1f to the timing at which writing is performed, and one period before one selection period. The period during which the polarity is reversed becomes slightly longer by the difference from the period from the start of the field period 1f to the timing at which writing is performed. As described above, the voltage applied to each pixel on each gate line is opposite in polarity to the voltage applied to the adjacent upper and lower pixels in almost one field period or two field periods in one frame period, and is the same in the remaining period. Because it can be a polarity, it is possible to reduce the occurrence of disclination lines, improve the contrast, improve the brightness,
Image quality can be greatly improved.

The difference from the first embodiment is that the lines selected at 2f and 3f in the four field periods are exchanged. By doing so, flicker can be reduced.

In the above embodiment, the method of applying a voltage to each pixel as shown in FIG. 5A has been described.
The polarity is inverted for each source line as shown in FIG.
Even if the polarity is inverted every two source lines as shown in FIG.

(Embodiment 4) This embodiment is a driving method in the case where the number of field periods divided into one frame period is changed to eight field periods by the same driving method as in the third embodiment.

FIG. 4 shows the case where the polarity of the voltage applied to the pixels in the scanning line direction is the same as shown in FIG. 5 (a), and the polarity of the voltage applied to each pixel when driving in eight fields is performed. FIG. 5 is a diagram showing timing of voltage writing, and is a timing chart of Y1 in FIG.
6 to Yn are diagrams showing the polarity of the voltage applied to each pixel on each of the gate lines Y1 to Yn in FIG. 6B and the timing of writing by turning on the transistor of each pixel. The polarity is the common electrode 608 in FIG.
08 denotes the transparent electrode 73 of FIG. ) Are shown as positive and negative with respect to the potential of FIG. Further, the diagram shown in FIG. 4 indicates the polarity of the voltage applied to each pixel, and does not indicate the voltage level actually applied. As the voltage actually applied to each pixel, voltages having different voltage levels are applied in accordance with display data.

In FIG. 4, 1F is the first frame and 2F is the second frame.
Represents the frame.

In the first frame, first, gate lines Y1, Y9,..., Yn-7 and 8 in the first field indicated by 1f.
Interlaced scanning is performed for each line, a selection is made, and writing is performed. Y1, Y17,..., Yn-7 (from Y1 to 1
Writing is performed with a positive polarity on the gate lines corresponding to every six lines), and writing is performed with a negative polarity on the Y9, Y25,... (Gate lines corresponding to every 16 lines from Y9).
The voltage on the positive polarity side is written into the pixel on the gate line Y1 during the one selection period at the timing of a, and is held until the timing of a 'of the second frame to be written next. Then, in the next selection period, the voltage on the negative polarity side is written into the pixel on the gate line Y9 at the timing of b during one selection period, and is held until the timing of b 'of the second frame to be written next. As described above, the polarity of the write voltage is inverted, and the polarity is sequentially selected by interlaced scanning for every eight lines, and the voltage is written to each pixel on the gate line Yn-7 and held until the next write. This ends one field period, and the second field indicated by the next 2f is started.

In the second field, the gate lines Y3, Y1
1,..., Yn-5 and interlaced scanning for every eight lines are performed, selection is made, and writing is performed. Y3, Y19, ...
·, Yn-5 (gate line corresponding to every 16 lines from Y3)
Are written with positive polarity, and Y11, Y27,.
(Gate lines corresponding to every 16 lines from Y11) are written with negative polarity. The voltage on the positive polarity side is written into the pixel on the gate line Y3 at the timing of c during one selection period, and is held until the timing of c 'of the second frame to be written next. Then, in the next selection period, the voltage on the negative polarity side is written to the pixel on the gate line Y11 at a timing delayed by one selection period from c during one selection period, and the pixel is written from c ′ of the second frame to be written next. The data is held until the timing delayed by one selection period. As described above, the polarity of the write voltage is inverted, and the polarity is sequentially selected by the interlaced scanning for every eight lines, and the voltage is written to each pixel on the gate line Yn-5 and held until the next write. This ends the two-field period, and the third field indicated by the next 3f is started.

In the third field, the gate lines Y2, Y1
.., Yn-6 and interlaced scanning for every eight lines are performed, selection is made, and writing is performed. Y2, Y18, ...
.., Yn-6 (gate line corresponding to every 16 lines from Y2)
Are written with positive polarity, and Y10, Y26,...
(Gate lines corresponding to every 16 lines from Y10) are written with negative polarity. The voltage on the positive polarity side is written to the pixel on the gate line Y2 during one selection period at the timing of d, and held until the next writing. In the next selection period, the voltage on the negative polarity side is written to the pixel on the gate line Y10 at the timing of e during one selection period, and is held until the next writing. In this way, selection is performed sequentially while inverting the polarity of the write voltage every eight lines,
The voltage is written to each pixel on the gate line Yn-6 and held until the next writing. This ends the three-field period, and the fourth field indicated by the next 4f starts.

In this manner, in the fourth field, interlaced scanning is performed for every eight lines with the gate lines Y4, Y12,..., Yn-4, and selection is made and writing is performed. Y
, Yn-4 (gate lines corresponding to every 16 lines from Y4) are written with positive polarity and Y1
2, Y28,... (Gate lines corresponding to every 16 lines from Y12) are written with negative polarity. Gate line Y
The voltage on the positive polarity side is written to the upper pixel 4 at the timing of f during one selection period, and held until the next writing. Then, a gate line is selected every eight lines, and while switching the polarity of the voltage applied to each pixel every selection period, a voltage is written to each pixel on the selected gate line and held until the next writing. .

In the fifth field, the gate lines Y5, Y1
3,..., Yn−3 and interlaced scanning for every eight lines are performed, selection is made, and writing is performed. Y5, Y21, ...
·, Yn-3 (gate line corresponding to every 16 lines from Y5)
Are written with positive polarity, and Y13, Y29,.
(Gate lines corresponding to every 16 lines from Y13) are written with negative polarity. The voltage on the positive polarity side is written into the pixel on the gate line Y5 at the timing of g during one selection period, and is held until the next writing. Then, a gate line is selected every eight lines, and while switching the polarity of the voltage applied to each pixel every selection period, a voltage is written to each pixel on the selected gate line and held until the next writing. .

In the sixth field, the gate lines Y7, Y1
5,..., Yn-1 and interlaced scanning for every 8 lines are performed, selection is made, and writing is performed. Y7, Y23, ...
.., Yn-1 (gate line corresponding to every 16 lines from Y7)
Are written with positive polarity, and Y15, Y31,...
(Gate lines corresponding to every 16 lines from Y15) are written with negative polarity. The voltage on the positive polarity side is written into the pixel on the gate line Y7 during one selection period at the timing of h, and is held until the next writing. Then, a gate line is selected every eight lines, and while switching the polarity of the voltage applied to each pixel every selection period, a voltage is written to each pixel on the selected gate line and held until the next writing. .

In the seventh field, the gate lines Y6, Y1
4,..., Yn-2 and interlaced scanning for every eight lines are performed, and selection is made and writing is performed. Y6, Y22, ...
.., Yn-2 (gate line corresponding to every 16 lines from Y6)
Are written with positive polarity, and Y14, Y30,...
(Gate lines corresponding to every 16 lines from Y14) are written with negative polarity. The voltage on the positive polarity side is written into the pixel on the gate line Y6 at the timing of i during one selection period, and held until the next writing. Then, a gate line is selected every eight lines, and while switching the polarity of the voltage applied to each pixel every selection period, a voltage is written to each pixel on the selected gate line and held until the next writing. .

In the eighth field, the gate lines Y8, Y1
6,..., Yn and interlaced scanning for every 8 lines are performed, and selection is made and writing is performed. Y8, Y24, ...,
Yn (gate line corresponding to every 16 lines from Y8) is written with positive polarity, and Y16, Y32,.
A gate line corresponding to every 16 to 16 lines) is written with negative polarity. The voltage on the positive polarity side is written to the pixel on the gate line Y8 at the timing of j during one selection period, and is held until the next writing. Then, a gate line is selected every eight lines, and while switching the polarity of the voltage applied to each pixel every selection period, a voltage is written to each pixel on the selected gate line and held until the next writing. .

In this way, the first frame ends after the eighth field is completed, and then the second frame is started.

In the second frame, a voltage is written to each pixel in the same manner as in the first frame, with a polarity opposite to that of the first frame. This operation is repeated, and each pixel is AC-driven.

By performing such driving, X1 to X1
The voltage applied to the source line indicated by Xm switches the polarity every selection period, for example, while the gate line Y shown in FIG.
2 with respect to the applied voltage of each pixel on the gate line Y
As for the voltage applied to each pixel on 1 in the first frame period in FIG. 4, almost two field periods (1f to 2f) in one frame period have the opposite polarity and the remaining period (3f to 8f). ) Have the same polarity. Then, the gate line Y2
For the applied voltage of each pixel above, the gate line Y3 below it
As for the voltage applied to each of the above pixels, when looking at the first frame period in FIG. 4, almost one field period (2f) in one frame period has the opposite polarity and the remaining periods (1f and 3f to 8f). Have the same polarity.

In addition, with respect to the voltage applied to each pixel on the gate line Y7 in FIG. 6B, the voltage applied to each pixel on the gate line Y6 thereover is different from the voltage applied in the first frame period in FIG. , Only one field period (6f) in one frame period has the opposite polarity and the remaining periods (1f to 5f and 7f)
f-8f) have the same polarity. Then, with respect to the voltage applied to each pixel on the gate line Y7, the voltage applied to each pixel on the gate line Y8 below the voltage applied to each pixel on the gate line Y7 in the first frame period in FIG. Almost only two field periods (6f to 7f) have opposite polarities and the remaining period (1f
5f and 8f) have the same polarity. Therefore, the total of the periods of the opposite polarity in the scanning lines on both sides adjacent to any one of the scanning lines is substantially equal to the three-field period (the two-field period on the upper side and the one-field period on the lower side). (However, in one field period 1f at the beginning of each frame period, for a gate line whose polarity is switched by interlaced scanning, writing is performed from the start of one field period 1f to the immediately preceding gate line. Until the time when it is performed, or one field period 1f
The period during which the polarity is reversed becomes slightly longer by the difference between the period from the start of writing to the timing at which writing is performed and the period from the start of one field period 1f, which is one selection period before, to the timing at which writing is performed. As described above, the voltage applied to each pixel on each gate line is opposite in polarity to the voltage applied to the adjacent upper and lower pixels in almost one field period or two field periods in one frame period, and is the same in the remaining period. Because it can be a polarity, it is possible to reduce the occurrence of disclination lines, improve the contrast, improve the brightness,
Image quality can be greatly improved. In addition, flicker can be reduced.

In the above embodiment, a method of applying a voltage to each pixel as shown in FIG. 5A has been described.
The polarity is inverted for each source line as shown in FIG.
Even if the polarity is inverted every two source lines as shown in FIG. (FIG. 5 shows Example 3
As shown in FIG. 7, the polarity is inverted every four pixels in the gate line direction in order to show a case where one frame period is divided into four fields to drive, but in the fourth embodiment, the polarity is inverted every eight pixels. change. (Example 5) Example 1 above
When the display quality was evaluated while changing the number of fields to be divided into one frame period by the driving method shown in FIGS.
It was confirmed that when the division was performed up to about 32 fields, the influence of the disclination was almost eliminated, and the reduction in luminance and contrast was eliminated.

Further, the control circuit of the liquid crystal display device becomes more complicated as the number of fields to be divided increases.

From these facts, it was possible to optimize the control circuit while improving the display quality such as luminance and contrast by setting the number of fields to be divided into the range of 2 to 32.

Embodiment 6 A liquid crystal projector using a reflective liquid crystal light valve according to the driving method described in Embodiments 1 to 5 above was manufactured and the image quality was evaluated.
Brightness and contrast were improved, and image quality was greatly improved.

Further, when a direct-view type liquid crystal display device using an amorphous silicon TFT was manufactured and the image quality was evaluated, the brightness and contrast were improved and the image quality was improved.
By incorporating this display device into a personal computer or a television, an electronic device with improved image quality and easy to see can be provided.

In the first, second, third, fourth, and sixth embodiments, the case where one frame period is divided into four fields and eight fields has been described as an example. The following integers may be used. Also, even when the number of scanning lines does not become an integral multiple of the number of fields, the number of scanning lines may be increased to an integral multiple including virtual scanning lines. You may go to.

Further, in the case of a liquid crystal mode other than the liquid crystal mode shown in the first to sixth embodiments, for example, a TN mode or a 45 ° twist TN mode, a similar driving method is used to reduce disclination lines and improve image quality. You can do it.

In the first to sixth embodiments, the reflection type liquid crystal light valve in which the liquid crystal driver is incorporated in the silicon substrate and each pixel is provided with a switching element by a MOS transistor has been described as an example.
In the case of an active matrix liquid crystal display device using a switching element such as an FT or polysilicon TFT, a similar driving method can reduce disclination lines and improve image quality. Also, an active matrix liquid crystal display device using a non-linear two-terminal element can be driven by the same concept.

[0093]

As described above, according to the liquid crystal display device of the present invention, the voltage applied to each pixel on each gate line is opposite in polarity to the voltage applied to each of the upper and lower adjacent pixels. Since only a part of the entire application period can be the same polarity during the rest, and the length of the period during which the voltage of the opposite polarity is applied can be almost the same for any line, The occurrence of disclination lines can be reduced, the contrast and luminance can be improved, flickering can be reduced, and image quality can be greatly improved.

Further, in the electronic apparatus of the present invention, brightness and contrast are improved, flicker is reduced, and the image quality of the liquid crystal display device is greatly improved, so that the electronic device can be easily viewed.

[Brief description of the drawings]

FIG. 1 is a diagram showing the polarity of a voltage applied to each pixel and the timing of voltage writing in one embodiment of the present invention.

FIG. 2 is a diagram showing the polarity of a voltage applied to each pixel and the timing of voltage writing in one embodiment of the present invention.

FIG. 3 is a diagram showing the polarity of a voltage applied to each pixel and the timing of voltage writing in one embodiment of the present invention.

FIG. 4 is a diagram showing the polarity of a voltage applied to each pixel and the timing of voltage writing in one embodiment of the present invention.

FIG. 5 is a diagram showing the polarity of a voltage applied to each pixel during a first frame period in one embodiment of the present invention.

FIG. 6 is a block diagram illustrating an example of a configuration of a driving circuit and pixels of an active matrix liquid crystal display device.

FIG. 7 is a cross-sectional view illustrating an example of the configuration of a reflective liquid crystal light valve.

FIG. 8 is a diagram showing a state of occurrence of a disclination line.

FIG. 9 is a diagram showing the polarity of a voltage applied to each pixel in the conventional driving.

[Explanation of symbols]

 601. Equivalent circuit of pixel section 602. Transistor 603. Gate 604. Source 605. Drain and pixel electrode 606. Liquid crystal 607. Retention capacity 608. Common electrode 611. Signal line driver 612. Gate line driver 613. Pixel portion 614. Gate line 615. Source line 71. Polarizing means 72. Glass substrate 73. Transparent electrode 74.76. Alignment film 75. Liquid crystal 77. Silicon substrate

Claims (8)

[Claims] In an active matrix type liquid crystal display device in which a switching element is provided in each pixel, the polarity of a voltage applied to each pixel on a first scanning line is adjacent to the first scanning line in one frame period. A liquid crystal display having a first period in which the polarity of a voltage applied to each pixel on a scanning line to be applied is opposite to a polarity of a common electrode and a second period in which the polarity is the same. How to drive the device. 2. A voltage applied to each pixel on a first scanning line is compared with a voltage applied to each pixel on a scanning line on both sides of the first scanning line, and the sum of the first period is 2. The driving method for a liquid crystal display device according to claim 1, wherein the same is applied to a scanning line. 3. One frame period is divided into N (N is an integer of 2 or more) sub-periods, and in each sub-period, the polarity of an applied voltage is inverted every scanning period while skipping every N scanning lines. 3. The method for driving a liquid crystal display device according to claim 1, wherein: 4. A frame period is divided into N (2 ≦ N ≦ 32 integer) sub-periods, and in each sub-period, the polarity of an applied voltage is inverted every scanning period while skipping every N scanning lines. 4. The method for driving a liquid crystal display device according to claim 3, wherein: 5. The driving method for a liquid crystal display device according to claim 3, wherein the order of scanning lines to be scanned is changed for each sub-selection period. 6. The driving method for a liquid crystal display device according to claim 1, wherein the polarities of the voltages applied to the pixels on the same scanning line are the same. 7. The liquid crystal according to claim 1, wherein the polarity of the voltage applied to each pixel on the same scanning line is opposite for each pixel or every two pixels based on the potential of the common electrode. A method for driving a display device. 8. An electronic apparatus comprising a liquid crystal display device using the driving method according to claim 1.