JP4142032B2 - Liquid crystal display device, driving method thereof, and electronic apparatus - Google Patents

Description

  The present invention relates to a driving method for a liquid crystal display device, and more particularly to a driving method for an active matrix liquid crystal display device. The present invention also relates to a liquid crystal display device using an active matrix liquid crystal display device driving method and an electronic apparatus including the liquid crystal display device.

As a driving method of a conventional active matrix liquid crystal display device, there is a driving method as described in Patent Document 1.
Japanese Patent Publication No. 5-29916

  This driving method includes a method of reversing the polarity of the voltage applied to each pixel for each scanning line as shown in FIG. 9A, and the polarity of the voltage applied to each pixel as shown in FIG. 9B. Is a driving method such as reversing each other. This driving method is mainly intended to prevent flickering of the screen and to improve display unevenness.

  In the case of such a driving method, the voltage applied to the adjacent pixels has a reverse polarity in most of the period of one frame, so that the voltage applied to the adjacent pixels as shown in FIG. If the polarity is reversed, a disclination line will be generated.

  For example, in the configuration of the reflective liquid crystal light valve shown in FIG. 7, 71 is a polarizing means, 72 is a glass substrate, 73 is a transparent electrode, 74 is an alignment film, 75 is a liquid crystal, 76 is an alignment film, 77 is a silicon substrate, A circuit as shown in FIG. 6 is formed on the silicon substrate 77, and the liquid crystal 75 becomes dark when a nematic liquid crystal having a negative dielectric anisotropy is placed in an inclined vertical alignment cell and no voltage is applied to the liquid crystal. The case of the liquid crystal mode will be described as an example.

  A white line is displayed by applying an ON voltage to each pixel, and the disclination line generated when the polarity of the voltage applied to the adjacent pixels is reversed becomes dark. The appearance of this disclination line is shown in FIG. 81 to 84 represent each pixel, and + and − represent the polarity of the voltage applied to each pixel. Reference numerals 85 to 88 denote the state of occurrence of disclination lines generated in each pixel. Thus, a dark disclination line is generated near the boundary line of each pixel. This disclination line causes a decrease in image quality such as a decrease in contrast and a decrease in luminance.

  As the resolution becomes higher and the size of one pixel becomes smaller as recently, the ratio of the generation area of the disclination line to the pixel area increases, and the deterioration of image quality becomes more serious.

  In particular, a light valve used for a liquid crystal projector or the like has a small screen size and is required to have high definition. Among them, in the case of a reflective liquid crystal light valve as shown in Japanese Patent Laid-Open No. 9-236814, the gap between the pixels is small and the pixel size is small, so the influence of the disclination line is large and the image quality is also good. It will decline.

  Further, in order not to generate the disclination line, it is possible to make the polarity of the voltage applied to all the pixels the same and only invert the polarity for each frame, but flickering occurs.

  The liquid crystal display device of the present invention is an active matrix type liquid crystal display device in which a switching element is provided for each pixel. The polarity of the voltage applied to each pixel on the first scanning line is the first scan in one frame period. A first period having a polarity opposite to a polarity of a voltage applied to each pixel on a scanning line adjacent to the line, and a second period having the same polarity with respect to the potential of the common electrode. To do.

  According to the above configuration, it is possible to reduce the occurrence of the disclination line that occurs when the polarity of the voltage applied to adjacent pixels is reversed, and to improve the brightness and contrast of the liquid crystal display device.

  Further, the voltage applied to each pixel on the first scanning line is compared with the voltage applied to each pixel on the scanning line on both sides of the first scanning line, and the total of the first period is determined to which scanning line. It is also characterized by almost the same.

  According to the above configuration, it is possible to reduce the occurrence of the disclination line that occurs when the polarity of the voltage applied to adjacent pixels is reversed, and to improve the brightness and contrast of the liquid crystal display device.

  One frame period is divided into N (N is an integer of 2 or more) sub-periods, and the polarity of the applied voltage is inverted for each scanning period while each sub-period skips every N scanning lines. To do.

  According to the above configuration, it is possible to reduce the occurrence of the disclination line that occurs when the polarity of the voltage applied to adjacent pixels is reversed, and to improve the brightness and contrast of the liquid crystal display device.

Further, one frame period is divided into N (integers of 2 ≦ N ≦ 32) sub-periods, and the polarity of the applied voltage is inverted for each scanning period while each sub-period jumps for every N scanning lines. And

  According to the above configuration, it is possible to reduce the occurrence of disclination lines that occur when the polarity of the voltage applied to adjacent pixels is reversed, improve the brightness and contrast of the liquid crystal display device, and optimize the control circuit. It has the effect of being able to.

Further, the order of scanning lines to be scanned is changed every sub selection period.
According to the above configuration, it is possible to reduce the occurrence of disclination lines that occur when the polarity of the voltage applied to adjacent pixels is reversed, improve the brightness and contrast of the liquid crystal display device, and reduce flicker. Has an effect.

Further, the polarity of the voltage applied to each pixel on the same scanning line is the same.
According to the above configuration, it is possible to reduce the occurrence of the disclination line that occurs when the polarity of the voltage applied to adjacent pixels is reversed, and to improve the brightness and contrast of the liquid crystal display device.

  In addition, the polarity of the voltage applied to each pixel on the same scanning line is reverse polarity with respect to the potential of the common electrode for each pixel or every two pixels.

  According to the above configuration, it is possible to reduce the occurrence of disclination lines that occur when the polarity of the voltage applied to adjacent pixels is reversed, improve the brightness and contrast of the liquid crystal display device, and reduce flicker. Has an effect.

Further, the liquid crystal display device of the present invention includes a plurality of scanning lines and source lines, a plurality of pixel electrodes provided corresponding to intersections of the scanning lines and the source lines, and a common electrode facing the plurality of pixel electrodes. And an active matrix type liquid crystal display device comprising a transistor provided corresponding to each of the plurality of pixel electrodes and turned on between the source line and the pixel electrode when the scanning line is selected. A positive polarity region in which the polarity of the voltage applied to the pixel electrode corresponding to a plurality of adjacent scanning lines within one frame period with respect to the potential of the common electrode is positive, and the positive polarity A negative polarity region that is not included in the region, is adjacent to each other, and has negative polarity in all the polarities applied to the pixel electrodes corresponding to the same number of scanning lines as the scanning lines included in the positive polarity region And Within one frame period, one scanning line included in each of the positive polarity region and the negative polarity region is alternately selected while skipping a predetermined number of the scanning lines. The polarity of the voltage applied to the pixel electrode corresponding to the scanning line is inverted and applied to each pixel electrode corresponding to an arbitrary first scanning line among the plurality of scanning lines within the one frame period. The polarity of the voltage with respect to the potential of the common electrode is the polarity of the voltage applied to each pixel electrode corresponding to the second scanning line that is adjacent to the first scanning line and is selected after the first scanning line. The period of being the same as is longer than the period of opposite polarity .
In addition, the scanning lines corresponding to the upper and lower ends of the positive and negative regions move downward for each selection period of the scanning lines.

  Further, when the scanning lines included in the positive polarity region and the negative polarity region are selected, a scanning line located at the upper end of the region is selected.

  An electronic apparatus according to the present invention includes the liquid crystal display device according to the present invention. According to the above configuration, it is possible to provide an electronic device that is bright, has high contrast, is easy to see, and has high display quality.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
The first to sixth embodiments are active matrices in which transistors are provided in each pixel as shown in FIG. 6, and the reflection type liquid crystal light valve shown in FIG. 7 will be described as an example.

  6A shows an example of an equivalent circuit of the pixel portion. 602 is a transistor, 603 is a transistor gate, 604 is a transistor source, 605 is a transistor drain and a pixel electrode, 606 is a liquid crystal, Reference numeral 607 denotes a storage capacitor, and 608 denotes a common electrode. (B) is a block diagram of an example of a drive circuit of an active matrix liquid crystal display device, in which 611 is a signal line driver, 612 is a gate line driver, Y1 to Yn are gate lines, and X1 to Xm are source lines. Show.

As shown in FIG. 6B, the gate 603 of each pixel indicated by 601 is connected to the gate line and the source 604 is connected to the source line.
FIG. 7 is a diagram showing an example of the configuration of a reflective liquid crystal light valve. 71 is a polarizing means, 72 is a glass substrate, 73 is a transparent electrode, 74 is an alignment film, 75 is a liquid crystal, 76 is an alignment film, 77 is A circuit as shown in FIG. 6 is formed on the silicon substrate 77 by the silicon substrate. The liquid crystal 75 will be described by taking an example of a liquid crystal mode in which nematic liquid crystal having a negative dielectric anisotropy is placed in a tilted vertical alignment cell and darkens when no voltage is applied to the liquid crystal.

  FIG. 1 shows the timing at which a voltage is written to the pixels in each scanning line direction of the display shown in FIG. 5A and the polarity of the voltage. When the polarities of the voltages applied to the pixels in the scanning line direction are the same, driving is performed in four fields, and Y1 to Yn in FIG. 1 are the pixels on the gate lines Y1 to Yn in FIG. 6B. The timing of writing with the transistor turned on and the state where the voltage is held with the same polarity after the writing is performed in one selection period are shown. The polarity of the voltage applied to each pixel is expressed as positive or negative with reference to the potential V of the common electrode 608 in FIG. 6 (the common electrode 608 indicates the transparent electrode 73 in FIG. 7).

In FIG. 1, 1F represents the first frame and 2F represents the second frame.
In the first frame, first, interlaced scanning is performed every four lines with the gate lines Y1, Y5, Y9,... Yn-3 in the first field indicated by 1f, and selection is made and writing is performed. . Y1, Y9,... (Gate lines corresponding to every 8 lines from Y1) are written with positive polarity, and Y5,..., Yn-3 (gate lines corresponding to every 8 lines from Y5) are Writing is performed with negative polarity. The voltage on the positive polarity side is written to the pixel on the gate line Y1 at the timing a during one selection period, and is held until the timing a ′ of the second frame to be written next. In the next selection period, the negative polarity side voltage is written to the pixels on the gate line Y5 at the timing b, and held until the timing b 'of the second frame to be written next. In the next selection period, the positive voltage is written to the pixel on the gate line Y9 at the timing c during the first selection period, and then held until the timing of c ′ of the second frame. . As described above, the polarity of the write voltage is reversed and the selection is sequentially performed by interlaced scanning every four lines, and the negative polarity side voltage is written to the gate line Yn-3 at the timing of d during one selection period. Until the timing of d ′ of the second frame to be written next. Thus, the one-field period (1f) ends, and the second field indicated by the next 2f starts.

  In the second field, interlaced scanning is performed every four lines of the gate lines Y2, Y6, Y10,... Yn-2, selection is made, and writing is performed. Y2, Y10,... (Gate lines corresponding to every 8 lines from Y2) are written with positive polarity, and Y6,..., Yn-2 (gate lines corresponding to every 8 lines from Y6) are Writing is performed with negative polarity. The voltage on the positive polarity side is written to the pixel on the gate line Y2 at the timing e during one selection period, and is held until the timing e 'of the second frame to be written next. In the next selection period, the negative polarity side voltage is written to the pixels on the gate line Y6 at the timing f during one selection period, and is held until the timing f 'of the second frame to be written next. In the next selection period, the positive voltage is written to the pixels on the gate line Y10 at the timing of g during the selection period until the timing of g ′ of the second frame to be written next. As described above, the polarity of the write voltage is reversed and the selection is sequentially performed by interlaced scanning every four lines, and the negative polarity side voltage is written to the gate line Yn-2 at the timing of h during one selection period. Until the timing of h ′ of the second frame to be written next. This ends the two-field period, and starts the third field indicated by the next 3f.

  In the third field, interlaced scanning is performed every four lines with the gate lines Y3, Y7, Y11,..., Yn-1, and selection is made and writing is performed. Y3, Y11,... (Gate lines corresponding to every 8 lines from Y3) are written with positive polarity, and Y7,..., Yn-1 (gate lines corresponding to every 8 lines from Y7) are written. Writing is performed with negative polarity. The voltage on the positive polarity side is written into the pixel on the gate line Y3 at the timing of i for one selection period, and is held until the timing of i 'of the second frame to be written next. In the next selection period, the negative polarity side voltage is written to the pixels on the gate line Y7 at the timing of j during the selection period and held until the timing of j 'of the second frame to be written next. Then, in the next selection period, the positive-side voltage is written to the pixels on the gate line Y11 at the timing delayed by one selection period from j, and from the second frame j ′ to be written next. Hold until the timing delayed by one selection period. As described above, the polarity of the write voltage is reversed and the selection is sequentially performed by interlaced scanning every four lines, and the negative polarity side voltage is written to the gate line Yn-1 at the timing of k for one selection period. Until the timing of k ′ of the second frame to be written next. Thus, the three-field period ends, and the fourth field indicated by the next 4f is started.

  In the fourth field, interlaced scanning is performed every four lines with the gate lines Y4, Y8, Y12..., Yn, selection is made, and writing is performed. Y4, Y12,... (Gate lines corresponding to every 8 lines from Y4) are written with positive polarity, and Y8,..., Yn (gate lines corresponding to every 8 lines from Y8) are negative. The writing is done. The voltage on the positive polarity side is written into the pixel on the gate line Y4 at the timing of 1 for one selection period and held until the timing of l 'of the second frame to be written next. In the next selection period, the negative polarity side voltage is written to the pixels on the gate line Y8 at the timing of m for one selection period, and is held until the timing of m ′ of the second frame to be written next. Then, in the next selection period, the positive-side voltage is written to the pixels on the gate line Y12 at the timing delayed by one selection period from m, and from the second frame m ′ to be written next. Hold until the timing delayed by one selection period. In this way, while the polarity of the write voltage is inverted, selection is performed sequentially by interlaced scanning every four lines, and the negative polarity side voltage is written to the gate line Yn at the timing of n during one selection period. Until the timing of n ′ of the second frame written in This ends the four field period, the first frame ends, and then the second frame starts.

  In the second frame, a voltage is written to each pixel with the opposite polarity to the first frame in the same manner as the first frame. Then, this operation is repeated and each pixel is AC driven.

  By performing such driving, the voltage applied to the source lines indicated by X1 to Xm is changed to the applied voltage of each pixel on the gate line Y2 in FIG. 6B, for example, while switching the polarity every selection period. On the other hand, when the voltage applied to each pixel on the gate line Y1 is viewed in the first frame period of FIG. 1, only one field period (1f) in one frame period remains in reverse polarity. This period (2f-4f) has the same polarity. Then, with respect to the voltage applied to each pixel on the gate line Y2, the voltage applied to each pixel on the gate line Y3 below the voltage applied to each pixel in the first frame period in FIG. Only one field period (2f) has the opposite polarity and the remaining periods (1f and 3f-4f) have the same polarity.

  Further, the voltage applied to each pixel on the gate line Y6 above the voltage applied to each pixel on the gate line Y7 in FIG. 6B is seen in the first frame period in FIG. Only one field period in one frame period (from the timing of f to the timing of j) has a reverse polarity and the remaining period (from the timing of 1f to f and from the timing of j to the end of 4f) has the same polarity. The voltage applied to each pixel on the gate line Y8 therebelow is almost one field period in one frame period (from timing j to timing m) in the first frame period in FIG. Only the reverse polarity and the remaining periods (from the timing of 1f to j and from the timing of m to the end of 4f) have the same polarity. Accordingly, the total period of the opposite polarity in the scanning lines on both sides adjacent to any scanning line is substantially equal to two field periods (one field period on each of the upper and lower sides). (However, in the one field period 1f at the beginning of each frame period, the gate line selected by switching the polarity by interlaced scanning is written from the start of the one field period 1f to the adjacent immediately preceding gate line. The period from the start of one field period 1f to the timing at which writing is performed and the period from the start of one field period 1f before one selection period to the timing at which writing is performed, (The period of reverse polarity is slightly longer.)

  As described above, the voltage applied to each pixel on each gate line may be opposite in polarity to the voltage applied to adjacent upper and lower pixels in only one field period in one frame period and the same polarity in the remaining period. Therefore, the occurrence of disclination lines can be reduced, the contrast and the brightness can be improved, and the image quality can be greatly improved.

  Although the above embodiment has been described by applying a voltage to each pixel as shown in FIG. 5A, the polarity is reversed for each source line as shown in FIG. As shown in c), even if the polarity is inverted every two source lines, the driving can be performed in the same manner.

  The diagram shown in FIG. 1 represents the polarity of the voltage applied to each pixel and does not represent the voltage level actually applied. As voltages actually applied to the respective pixels, voltages having different voltage levels are applied in accordance with display data.

  In this embodiment, the driving method is the same as that in the first embodiment, and the number of field periods divided into one frame period is changed to 8 field periods.

  FIG. 2 shows the timing at which the voltage is written to the pixels in the respective scanning line directions of the display shown in FIG. 5A and the polarity of the voltage. When the polarities of the voltages applied to the pixels in the scanning line direction are the same, driving is performed in 8 fields. Y1 to Yn in FIG. 2 are transistors of the pixels on the gate lines Y1 to Yn in FIG. 6B. The timing at which is turned on and the voltage is held with the same polarity after the writing is performed in one selection period is shown. The polarity of the voltage applied to each pixel is expressed as positive or negative with reference to the potential V of the common electrode 608 in FIG. 6 (the common electrode 608 indicates the transparent electrode 73 in FIG. 7).

In FIG. 2, 1F represents the first frame and 2F represents the second frame.
In the first frame, first, interlace scanning is performed every eight lines with the gate lines Y1, Y9,..., Yn-7 in the first field indicated by 1f, selection is made, and writing is performed. Y1, Y17,..., Yn-7 (gate lines corresponding to every 16 lines from Y1) are written with positive polarity, and Y9, Y25,... (Gate lines corresponding to every 16 lines from Y9) ) Is written in a negative polarity. The voltage on the positive polarity side is written to the pixel on the gate line Y1 at the timing a during one selection period, and is held until the timing a ′ of the second frame to be written next. In the next selection period, the negative polarity side voltage is written to the pixels on the gate line Y9 at the timing b, and held until the timing b 'of the second frame to be written next. In this manner, the polarity of the write voltage is reversed and the selection is sequentially performed by interlaced scanning every 8 lines, and the voltage is written to each pixel on the gate line Yn-7 and held until the next write. Thus, the one field period ends, and the second field indicated by 2f is started.

  In the second field, interlaced scanning is performed every eight lines with the gate lines Y2, Y10,..., Yn-6, selection is made, and writing is performed. Y2, Y18,..., Yn-6 (gate lines corresponding to every 16 lines from Y2) are written with positive polarity, and Y10, Y26,... (Gate lines corresponding to every 16 lines from Y10) ) Is written in a negative polarity. The voltage on the positive polarity side is written into the pixel on the gate line Y2 at the timing c for one selection period, and is held until the timing c 'of the second frame to be written next. In the next selection period, the negative polarity side voltage is written to the pixels on the gate line Y10 at the timing d during one selection period, and is held until the timing d 'of the second frame to be written next. In this manner, the polarity of the write voltage is reversed and the selection is sequentially performed by interlaced scanning every 8 lines, and the voltage is written to each pixel on the gate line Yn-6 and held until the next write. Thus, the two-field period ends, and the third field indicated by the next 3f is started.

  In this manner, in the third field, interlaced scanning is performed every eight lines with the gate lines Y3, Y11,..., Yn-5, and selection is made and writing is performed. Y3, Y19,..., Yn-5 (gate lines corresponding to every 16 lines from Y3) are written with positive polarity, and Y11, Y27,... (Gate lines corresponding to every 16 lines from Y11) ) Is written in a negative polarity. The voltage on the positive polarity side is written into the pixel on the gate line Y3 at the timing e during one selection period, and is held until the timing e 'of the second frame to be written next. Then, a gate line is selected by interlaced scanning every 8 lines, and the voltage is written to each pixel on the selected gate line while switching the polarity of the voltage applied to each pixel every selection period. Hold up.

  In the fourth field, interlaced scanning is performed every eight lines with the gate lines Y4, Y12,..., Yn-4, and selection is made and writing is performed. Y4, Y20,..., Yn-4 (gate lines corresponding to every 16 lines from Y4) are written with positive polarity, and Y12, Y28,... (Gate lines corresponding to every 16 lines from Y12) ) Is written in a negative polarity. The voltage on the positive polarity side is written into the pixel on the gate line Y4 at the timing f during one selection period, and is held until the timing f 'of the second frame to be written next. Then, the gate line is selected by interlaced scanning every 8 lines, and the voltage is written to each pixel on the selected gate line while the polarity of the voltage applied to each pixel is switched for each selection period. Hold up.

  In the fifth field, interlaced scanning is performed every eight lines with the gate lines Y5, Y13,..., Yn-3, selection is made, and writing is performed. Y5, Y21,..., Yn-3 (gate lines corresponding to every 16 lines from Y5) are written with positive polarity, and Y13, Y29,... (Gate lines corresponding to every 16 lines from Y13) ) Is written in a negative polarity. The voltage on the positive polarity side is written in the pixel on the gate line Y5 at the timing of g for one selection period and held until the timing of g ′ of the second frame to be written next. Then, the gate line is selected by interlaced scanning every 8 lines, and the voltage is written to each pixel on the selected gate line while the polarity of the voltage applied to each pixel is switched for each selection period. Hold up.

  In the sixth field, interlaced scanning is performed every eight lines with the gate lines Y6, Y14,..., Yn-2, and selection is made and writing is performed. Y6, Y22,..., Yn-2 (gate lines corresponding to every 16 lines from Y6) are written with positive polarity, and Y14, Y30,... (Gate lines corresponding to every 16 lines from Y14) ) Is written in a negative polarity. The voltage on the positive polarity side is written into the pixel on the gate line Y6 at the timing of h for one selection period and held until the timing of h ′ of the second frame to be written next. Then, the gate line is selected by interlaced scanning every 8 lines, and the voltage is written to each pixel on the selected gate line while the polarity of the voltage applied to each pixel is switched for each selection period. Hold up.

  In the seventh field, interlaced scanning is performed every eight lines with the gate lines Y7, Y15,..., Yn-1, and selection is made and writing is performed. Y7, Y23,..., Yn-1 (gate lines corresponding to every 16 lines from Y7) are written with positive polarity, and Y15, Y31, ... (gate lines corresponding to every 16 lines from Y15). ) Is written in a negative polarity. The voltage on the positive polarity side is written into the pixel on the gate line Y7 at the timing of i for one selection period and held until the timing of i 'of the second frame to be written next. Then, the gate line is selected by interlaced scanning every 8 lines, and the voltage is written to each pixel on the selected gate line while the polarity of the voltage applied to each pixel is switched for each selection period. Hold up.

  In the eighth field, interlace scanning is performed every eight lines with the gate lines Y8, Y16,..., Yn, selection is made, and writing is performed. Y8, Y24,..., Yn (gate lines corresponding to every 16 lines from Y8) are written with positive polarity, and Y16, Y32,... (Gate lines corresponding to every 16 lines from Y16) are Writing is performed with negative polarity. The voltage on the positive polarity side is written into the pixel on the gate line Y8 at the timing of j for one selection period and held until the timing of j 'of the second frame to be written next. Then, a gate line is selected by interlaced scanning every 8 lines, and the voltage is written to each pixel on the selected gate line while switching the polarity of the voltage applied to each pixel every selection period. Hold up.

  In this way, the process reaches the eighth field, the first frame is completed, and then the second frame is started.

  In the second frame, a voltage is written to each pixel with the opposite polarity to the first frame in the same manner as the first frame. Then, this operation is repeated and each pixel is AC driven.

  By driving in this way, the voltage applied to the source lines indicated by X1 to Xm is changed to the applied voltage of each pixel on the gate line Y2 in FIG. On the other hand, when the voltage applied to each pixel on the gate line Y1 is viewed in the first frame period of FIG. 2, only one field period (1f) in one frame period remains in reverse polarity. This period (2f-8f) has the same polarity. Then, with respect to the voltage applied to each pixel on the gate line Y2, the voltage applied to each pixel on the gate line Y3 below the voltage applied to each pixel in the first frame period in FIG. Only approximately one field period (2f) has a reverse polarity and the remaining periods (1f and 3f to 8f) have the same polarity.

  Further, when the voltage applied to each pixel on the gate line Y6 above the voltage applied to each pixel on the gate line Y7 in FIG. 6B is viewed in the first frame period in FIG. Only one field period (6f) in one frame period has a reverse polarity and the remaining periods (1f to 5f and 7f to 8f) have the same polarity. Then, with respect to the voltage applied to each pixel on the gate line Y7, the voltage applied to each pixel on the gate line Y8 below the voltage applied to each pixel in the first frame period in FIG. Only one field period (7f) has the opposite polarity and the remaining periods (1f-6f and 8f) have the same polarity. Accordingly, the total period of the opposite polarity in the scanning lines on both sides adjacent to any scanning line is substantially equal to two field periods (one field period on each of the upper and lower sides). (However, in the one field period 1f at the beginning of each frame period, the gate line selected by switching the polarity by interlaced scanning is written from the start of the one field period 1f to the adjacent immediately preceding gate line. The period from the start of one field period 1f to the timing at which writing is performed and the period from the start of one field period 1f before one selection period to the timing at which writing is performed, (The period of reverse polarity is slightly longer.)

  As described above, the voltage applied to each pixel on each gate line may be opposite in polarity to the voltage applied to adjacent upper and lower pixels in only one field period in one frame period and the same polarity in the remaining period. Therefore, the occurrence of disclination lines can be reduced, the contrast and the brightness can be improved, and the image quality can be greatly improved.

  Although the above embodiment has been described by applying a voltage to each pixel as shown in FIG. 5A, the polarity is reversed for each source line as shown in FIG. As shown in c), even if the polarity is inverted every two source lines, the driving can be performed in the same manner. (FIG. 5 shows a case in which one frame period is divided into four fields as shown in the first embodiment, and therefore the polarity is inverted every four pixels in the gate line direction. (Changes to polarity reversal by 8 pixels.)

  Also, the diagram shown in FIG. 2 represents the polarity of the voltage applied to each pixel as in FIG. 1 used in the description of the first embodiment, and does not represent the voltage level actually applied. As voltages actually applied to the respective pixels, voltages having different voltage levels are applied in accordance with display data.

FIG. 3 shows a diagram according to the third embodiment in FIG.
The diagram shown in FIG. 3 represents the polarity of the voltage applied to each pixel as in FIGS. 1 and 2 used in the description of the first and second embodiments, and does not represent the voltage level actually applied. As voltages actually applied to the respective pixels, voltages having different voltage levels are applied in accordance with display data. Further, the polarity of the voltage applied to each pixel is expressed as positive or negative with reference to the potential V of the common electrode 608 in FIG. 6 (the common electrode 608 indicates the transparent electrode 73 in FIG. 7).

In FIG. 3, 1F represents the first frame and 2F represents the second frame.
In the first frame, first, interlace scanning is performed every four lines with the gate lines Y1, Y5, Y9,..., Yn-3 in the first field indicated by 1f, and selection is made and writing is performed. Y1, Y9,... (Gate lines corresponding to every 8 lines from Y1) are written with positive polarity, and Y5,..., Yn-3 (gate lines corresponding to every 8 lines from Y5) are Writing is performed with negative polarity. The voltage on the positive polarity side is written to the pixel on the gate line Y1 at the timing a during one selection period, and is held until the timing a ′ of the second frame to be written next. In the next selection period, the negative polarity side voltage is written to the pixels on the gate line Y5 at the timing b, and held until the timing b 'of the second frame to be written next. In the next selection period, the positive polarity side voltage is written to the pixels on the gate line Y9 at the timing c during one selection period, and is held until the timing c ′ of the second frame to be written next. As described above, the polarity of the writing voltage is reversed and the selection is sequentially performed by interlaced scanning every four lines, and the negative polarity side voltage is written to the gate line Yn-3 at the timing of d during one selection period. It holds until the timing of d ′ of the second frame to be written next. Thus, the one field period ends, and the second field indicated by the next 2f is started.

  In the second field, interlaced scanning is performed every four lines with the gate lines Y3, Y7, Y11,..., Yn-1, selection is made, and writing is performed. Y3, Y11,... (Gate lines corresponding to every 8 lines from Y3) are written with positive polarity, and Y7,..., Yn-1 (gate lines corresponding to every 8 lines from Y7) are written. Writing is performed with negative polarity. The voltage on the positive polarity side is written into the pixel on the gate line Y3 at the timing e during one selection period, and is held until the timing e 'of the second frame to be written next. In the next selection period, the negative polarity side voltage is written to the pixels on the gate line Y7 at the timing of f during the first selection period, and is held until the timing of f ′ of the second frame to be written next. Then, in the next selection period, the voltage on the positive polarity side is written to the pixels on the gate line Y11 at the timing delayed by one selection period from f, and from the second frame f ′ written next. Hold until the timing delayed by one selection period. In this way, every four lines are sequentially selected while inverting the polarity of the write voltage, and the negative polarity side voltage is written to the gate line Yn-1 at the timing of g for one selection period and then written. Until the timing of the second frame g ′. Thus, the two-field period ends, and the third field indicated by the next 3f is started.

  In the third field, interlaced scanning is performed every four lines with the gate lines Y2, Y6, Y10,..., Yn-2, selection is made, and writing is performed. Y2, Y10,... (Gate lines corresponding to every 8 lines from Y2) are written with positive polarity, and Y6,..., Yn-2 (gate lines corresponding to every 8 lines from Y6) are Writing is performed with negative polarity. The voltage on the positive polarity side is written into the pixel on the gate line Y2 at the timing of h for one selection period and held until the timing of h 'of the second frame to be written next. Then, in the next selection period, the negative polarity side voltage is written to the pixels on the gate line Y6 at the timing i for one selection period, and is held until the timing i 'of the second frame to be written next. In the next selection period, the voltage on the positive polarity side is written to the pixels on the gate line Y10 at the timing of j during the selection period and held until the timing of j ′ of the second frame to be written next. As described above, the polarity of the write voltage is reversed and the selection is sequentially performed by interlaced scanning every four lines, and the negative polarity side voltage is written to the gate line Yn-2 at the timing of k for one selection period. It holds until the timing of k ′ of the second frame to be written next. Thus, the three-field period ends, and the fourth field indicated by the next 4f is started.

  In the fourth field, interlaced scanning is performed every four lines with the gate lines Y4, Y8, Y12..., Yn, selection is made, and writing is performed. Y4, Y12,... (Gate lines corresponding to every 8 lines from Y4) are written with positive polarity, and Y8,..., Yn (gate lines corresponding to every 8 lines from Y8) are negative. The writing is done. The voltage on the positive polarity side is written into the pixel on the gate line Y4 at the timing of 1 for one selection period and held until the timing of l 'of the second frame to be written next. In the next selection period, the negative polarity side voltage is written to the pixels on the gate line Y8 at the timing of m for one selection period, and is held until the timing of m ′ of the second frame to be written next. Then, in the next selection period, the positive-side voltage is written to the pixels on the gate line Y12 at the timing delayed by one selection period from m, and from the second frame m ′ to be written next. Hold until the timing delayed by one selection period. As described above, the polarity of the writing voltage is reversed and the selection is sequentially performed by interlaced scanning every four lines, and the negative polarity side voltage is written to the gate line Yn at the timing of n during one selection period. It holds until the timing of n ′ of the second frame to be written. This ends the four field period, the first frame ends, and then the second frame starts.

  In the second frame, a voltage is written to each pixel with the opposite polarity to the first frame in the same manner as the first frame. Then, this operation is repeated and each pixel is AC driven.

  By driving in this way, the voltage applied to the source lines indicated by X1 to Xm is changed to the applied voltage of each pixel on the gate line Y2 in FIG. On the other hand, when the voltage applied to each pixel on the gate line Y1 is viewed in the first frame period of FIG. 3, only about two field periods (1f to 2f) in one frame period are opposite in polarity. The remaining periods (3f to 4f) have the same polarity. Then, the voltage applied to each pixel on the gate line Y3 below it is the voltage applied to each pixel on the gate line Y2 in the first frame period of FIG. Only one field period (2f) has the opposite polarity and the remaining periods (1f and 3f-4f) have the same polarity.

  In addition, when the voltage applied to each pixel on the gate line Y6 is higher than the voltage applied to each pixel on the gate line Y7 in FIG. Only approximately one field period (from the timing of f to the timing of i) in one frame period has a reverse polarity and the remaining period (from the timings of 1f to i and from the timing of i to the end of 4f) has the same polarity. The voltage applied to each pixel on the gate line Y8 therebelow is approximately two field periods in one frame period (from the timing of f to the timing of m) in the first frame period of FIG. Only the reverse polarity and the remaining period (from the timings 1f to f and the timing m to the end of 4f) are the same polarity. Therefore, the total of the periods having opposite polarities on the scanning lines on both sides adjacent to any scanning line is substantially equal to the three field periods (two field periods on the upper side and one field period on the lower side). (However, in the one field period 1f at the beginning of each frame period, the gate line selected by switching the polarity by interlaced scanning is written from the start of the one field period 1f to the adjacent immediately preceding gate line. The period from the start of one field period 1f to the timing at which writing is performed and the period from the start of one field period 1f before one selection period to the timing at which writing is performed, (The period of reverse polarity is slightly longer.)

  As described above, the voltage applied to each pixel on each gate line is opposite to the voltage applied to each adjacent upper and lower pixels, and almost the same polarity in the remaining period, with only one or two field periods in one frame period being opposite in polarity. Therefore, the occurrence of disclination lines can be reduced, the contrast and the brightness can be improved, and the image quality can be greatly improved.

  The difference from the first embodiment is that the lines selected in 2f and 3f in the four field periods are switched. By doing so, flicker can be reduced.

  Although the above embodiment has been described by applying a voltage to each pixel as shown in FIG. 5A, the polarity is reversed for each source line as shown in FIG. As shown in c), even if the polarity is inverted every two source lines, the driving can be performed in the same manner.

  In this embodiment, the driving method is the same as that in the third embodiment. In this driving method, the number of field periods divided into one frame period is changed to 8 field periods.

  FIG. 4 shows the case where the polarity of the voltage applied to the pixels in the scanning line direction is the same as shown in FIG. 5A, and the polarity of the voltage applied to each pixel and the voltage writing when driving divided into 8 fields. 4 is a timing chart, and Y1 to Yn in FIG. 4 indicate the polarity of the voltage applied to each pixel on each of the gate lines Y1 to Yn in FIG. 6B and the timing at which the transistor of each pixel is turned on for writing. In the figure, the polarity of the voltage applied to each pixel is expressed as positive or negative with reference to the potential of the common electrode 608 in FIG. 6 (the common electrode 608 indicates the transparent electrode 73 in FIG. 7). The diagram shown in FIG. 4 represents the polarity of the voltage applied to each pixel, and does not represent the voltage level actually applied. As voltages actually applied to the respective pixels, voltages having different voltage levels are applied in accordance with display data.

In FIG. 4, 1F represents the first frame and 2F represents the second frame.
In the first frame, first, interlace scanning is performed every eight lines with the gate lines Y1, Y9,..., Yn-7 in the first field indicated by 1f, selection is made, and writing is performed. Y1, Y17,..., Yn-7 (gate lines corresponding to every 16 lines from Y1) are written with positive polarity, and Y9, Y25,... (Gate lines corresponding to every 16 lines from Y9) ) Is written in a negative polarity. The voltage on the positive polarity side is written to the pixel on the gate line Y1 at the timing a during one selection period, and is held until the timing a ′ of the second frame to be written next. In the next selection period, the negative polarity side voltage is written to the pixels on the gate line Y9 at the timing b, and held until the timing b 'of the second frame to be written next. In this manner, the polarity of the write voltage is reversed and the selection is sequentially performed by interlaced scanning every 8 lines, and the voltage is written to each pixel on the gate line Yn-7 and held until the next write. Thus, the one field period ends, and the second field indicated by 2f is started.

  In the second field, interlaced scanning is performed every eight lines with the gate lines Y3, Y11,..., Yn-5, selection is made, and writing is performed. Y3, Y19,..., Yn-5 (gate lines corresponding to every 16 lines from Y3) are written with positive polarity, and Y11, Y27,... (Gate lines corresponding to every 16 lines from Y11) ) Is written in a negative polarity. The voltage on the positive polarity side is written into the pixel on the gate line Y3 at the timing c for one selection period, and is held until the timing c 'of the second frame to be written next. In the next selection period, the negative polarity side voltage is written to the pixels on the gate line Y11 at the timing delayed by one selection period from c, and the second frame c ′ to be written next. Hold until the timing delayed by one selection period. In this way, the polarity of the write voltage is reversed and the selection is sequentially performed by interlaced scanning every 8 lines, and the voltage is written to each pixel on the gate line Yn-5 and held until the next write. Thus, the two-field period ends, and the third field indicated by the next 3f is started.

  In the third field, interlaced scanning is performed every eight lines with the gate lines Y2, Y10,..., Yn-6, selection is made, and writing is performed. Y2, Y18,..., Yn-6 (gate lines corresponding to every 16 lines from Y2) are written with positive polarity, and Y10, Y26,... (Gate lines corresponding to every 16 lines from Y10) ) Is written in a negative polarity. The voltage on the positive polarity side is written in the pixel on the gate line Y2 at the timing of d during one selection period and is held until the next writing. In the next selection period, the negative polarity side voltage is written in the pixel on the gate line Y10 at the timing e during one selection period and is held until the next writing. In this way, selection is performed sequentially while inverting the polarity of the write voltage every 8 lines, and the voltage is written to each pixel on the gate line Yn-6 and held until the next write. Thus, the three-field period ends, and the fourth field indicated by the next 4f starts.

  In this way, in the fourth field, interlaced scanning is performed every eight lines with the gate lines Y4, Y12,..., Yn-4, and selection is made and writing is performed. Y4, Y20,..., Yn-4 (gate lines corresponding to every 16 lines from Y4) are written with positive polarity, and Y12, Y28,... (Gate lines corresponding to every 16 lines from Y12) ) Is written in a negative polarity. The voltage on the positive polarity side is written into the pixel on the gate line Y4 at the timing of f for one selection period and held until the next writing. Then, a gate line is selected every 8 lines, and the voltage applied to each pixel is switched for each selection period, and the voltage is written to each pixel on the selected gate line and held until the next writing. .

  In the fifth field, interlaced scanning is performed every eight lines with the gate lines Y5, Y13,..., Yn-3, selection is made, and writing is performed. Y5, Y21,..., Yn-3 (gate lines corresponding to every 16 lines from Y5) are written with positive polarity, and Y13, Y29,... (Gate lines corresponding to every 16 lines from Y13) ) Is written in a negative polarity. The voltage on the positive polarity side is written in the pixel on the gate line Y5 at the timing of g for one selection period and held until the next writing. Then, a gate line is selected every 8 lines, and the voltage applied to each pixel is switched for each selection period, and the voltage is written to each pixel on the selected gate line and held until the next writing. .

  In the sixth field, interlaced scanning is performed every eight lines with the gate lines Y7, Y15,..., Yn-1, and selection is made and writing is performed. Y7, Y23,..., Yn-1 (gate lines corresponding to every 16 lines from Y7) are written with positive polarity, and Y15, Y31, ... (gate lines corresponding to every 16 lines from Y15). ) Is written in a negative polarity. The voltage on the positive polarity side is written to the pixel on the gate line Y7 at the timing of h for one selection period and held until the next writing. Then, a gate line is selected every 8 lines, and the voltage applied to each pixel is switched for each selection period, and the voltage is written to each pixel on the selected gate line and held until the next writing. .

  In the seventh field, interlaced scanning is performed every eight lines with the gate lines Y6, Y14,..., Yn-2, and selection is made and writing is performed. Y6, Y22,..., Yn-2 (gate lines corresponding to every 16 lines from Y6) are written with positive polarity, and Y14, Y30,... (Gate lines corresponding to every 16 lines from Y14) ) Is written in a negative polarity. The voltage on the positive polarity side is written in the pixel on the gate line Y6 at the timing of i for one selection period and held until the next writing. Then, a gate line is selected every 8 lines, and the voltage applied to each pixel is switched for each selection period, and the voltage is written to each pixel on the selected gate line and held until the next writing. .

  In the eighth field, interlace scanning is performed every eight lines with the gate lines Y8, Y16,..., Yn, selection is made, and writing is performed. Y8, Y24,..., Yn (gate lines corresponding to every 16 lines from Y8) are written with positive polarity, and Y16, Y32,... (Gate lines corresponding to every 16 lines from Y16) are written. Writing is performed with negative polarity. The voltage on the positive polarity side is written in the pixel on the gate line Y8 at the timing of j for one selection period and held until the next writing. Then, a gate line is selected every 8 lines, and the voltage applied to each pixel is switched for each selection period, and the voltage is written to each pixel on the selected gate line and held until the next writing. .

  In this way, the process reaches the eighth field, the first frame is completed, and then the second frame is started.

  In the second frame, a voltage is written to each pixel with the opposite polarity to the first frame in the same manner as the first frame. Then, this operation is repeated and each pixel is AC driven.

  By driving in this way, the voltage applied to the source lines indicated by X1 to Xm is changed to the applied voltage of each pixel on the gate line Y2 in FIG. On the other hand, when the voltage applied to each pixel on the gate line Y1 is viewed in the first frame period of FIG. 4, only about two field periods (1f to 2f) in one frame period are opposite in polarity. The remaining periods (3f to 8f) have the same polarity. Then, with respect to the voltage applied to each pixel on the gate line Y2, the voltage applied to each pixel on the gate line Y3 below the voltage applied to each pixel in the first frame period in FIG. Only approximately one field period (2f) has a reverse polarity and the remaining periods (1f and 3f to 8f) have the same polarity.

  Further, when the voltage applied to each pixel on the gate line Y6 above the voltage applied to each pixel on the gate line Y7 in FIG. 6B is viewed in the first frame period in FIG. Only one field period (6f) in one frame period has a reverse polarity and the remaining periods (1f to 5f and 7f to 8f) have the same polarity. Then, with respect to the voltage applied to each pixel on the gate line Y7, the voltage applied to each pixel on the gate line Y8 below the voltage applied to each pixel in the first frame period in FIG. Only approximately two field periods (6f-7f) have opposite polarity and the remaining periods (1f-5f and 8f) have the same polarity. Therefore, the total of the periods having opposite polarities on the scanning lines on both sides adjacent to any scanning line is substantially equal to the three field periods (two field periods on the upper side and one field period on the lower side). (However, in the one field period 1f at the beginning of each frame period, the gate line selected by switching the polarity by interlaced scanning is written from the start of the one field period 1f to the adjacent immediately preceding gate line. The period from the start of one field period 1f to the timing at which writing is performed and the period from the start of one field period 1f before one selection period to the timing at which writing is performed, (The period of reverse polarity is slightly longer.)

  As described above, the voltage applied to each pixel on each gate line is opposite to the voltage applied to each adjacent upper and lower pixels, and almost the same polarity in the remaining period, with only one or two field periods in one frame period being opposite in polarity. Therefore, the occurrence of disclination lines can be reduced, the contrast and the brightness can be improved, and the image quality can be greatly improved. Further, flicker can be reduced.

  Although the above embodiment has been described by applying a voltage to each pixel as shown in FIG. 5A, the polarity is reversed for each source line as shown in FIG. As shown in c), even if the polarity is inverted every two source lines, the driving can be performed in the same manner. (FIG. 5 shows a case in which one frame period is divided into four fields for driving as shown in the third embodiment. Therefore, the polarity is reversed every four pixels in the gate line direction. (Changes to polarity reversal by 8 pixels.)

  When the display quality was evaluated while changing the number of fields divided into one frame period by the driving methods shown in the first to fourth embodiments, when dividing up to about 32 fields, the influence of disclination was almost eliminated. It was confirmed that the decrease in brightness and contrast was eliminated.

Further, the control circuit of the liquid crystal display device becomes more complicated as the number of divided fields increases.
Therefore, by optimizing the number of fields to be divided within the range of 2 to 32, it is possible to optimize the control circuit while improving the display quality such as brightness and contrast.

  When a liquid crystal projector using a reflection type liquid crystal light valve by the driving method shown in Examples 1 to 5 was manufactured and image quality was evaluated, the brightness and contrast were improved, and the image quality was greatly improved. .

  In addition, when a direct-view type liquid crystal display device using amorphous silicon TFTs was fabricated and image quality was evaluated, brightness and contrast were improved and image quality was improved. By incorporating this display device into a personal computer or a television, an electronic device with improved image quality and easy viewing can be provided.

  In the first, second, third, fourth, and sixth embodiments, the case where one frame period is divided into four fields and eight fields is described as an example. If it is. Even when the number of scanning lines does not become an integral multiple of the number of fields, it may be an integer multiple including the virtual scanning lines. When the last scanning line selected for each field is selected, the next field is selected. You can also go to.

  In addition to the liquid crystal modes shown in the first to sixth embodiments, for example, the TN mode and the 45-degree twisted TN mode, the same drive method can be used to reduce the disclination line and improve the image quality. it can.

In the first to sixth embodiments, the liquid crystal driver is incorporated in the silicon substrate and the reflection type liquid crystal light valve in which the switching element by the MOS transistor is attached to each pixel has been described as an example. However, the amorphous silicon TFT and the polysilicon TFT are described. In the case of an active matrix liquid crystal display device using such switching elements, the image quality can be improved by reducing the disclination line by the same driving method. An active matrix liquid crystal display device using a non-linear two-terminal element can also be driven in the same way.

The figure which shows the polarity of the voltage applied to each pixel in one Example of this invention, and the timing of voltage writing. The figure which shows the polarity of the voltage applied to each pixel in one Example of this invention, and the timing of voltage writing. The figure which shows the polarity of the voltage applied to each pixel in one Example of this invention, and the timing of voltage writing. The figure which shows the polarity of the voltage applied to each pixel in one Example of this invention, and the timing of voltage writing. The figure which shows the polarity of the voltage applied to each pixel in the 1st frame period in one Example of this invention. FIG. 10 is a block diagram illustrating an example of a structure of a driver circuit and pixels of an active matrix liquid crystal display device. Sectional drawing which shows an example of a structure of a reflection type liquid crystal light valve. The figure which shows the mode of generation | occurrence | production of a disclination line. The figure which shows the polarity of the voltage applied to each pixel by the conventional drive.

Explanation of symbols

601. Pixel equivalent circuit 602. Transistor 603. Gate 604. Source 605. Drain and pixel electrode 606. Liquid crystal 607. Retention capacity 608. Common electrode 611. Signal line driver 612. Gate line driver 613. Pixel unit 614. Gate line 615. Source line 71. Polarization means 72. Glass substrate 73. Transparent electrode 74.76. Alignment film 75. Liquid crystal 77. Silicon substrate

Claims (5)

A plurality of scan lines and source lines;
A plurality of pixel electrodes provided corresponding to the intersection of the scanning line and the source line;
A common electrode facing the plurality of pixel electrodes;
A transistor provided corresponding to each of the plurality of pixel electrodes and turned on between the source line and the pixel electrode when the scanning line is selected;
An active matrix liquid crystal display device comprising:
A positive polarity region in which the polarity of the voltage applied to the pixel electrode corresponding to a plurality of adjacent scanning lines within one frame period with respect to the potential of the common electrode is all positive,
The polarities of the voltages applied to the pixel electrodes that are not included in the positive polarity region, are adjacent to each other, and correspond to the same number of scanning lines as the scanning lines included in the positive polarity region are all negative. And a negative polarity region,
Within one frame period, one scanning line included in each of the positive polarity region and the negative polarity region is alternately selected while skipping a predetermined number of the scanning lines, and the selected scanning line is selected. The polarity of the voltage applied to the pixel electrode corresponding to is inverted ,
Within the one frame period, the polarity of the voltage applied to each pixel electrode corresponding to an arbitrary first scanning line among the plurality of scanning lines with respect to the potential of the common electrode is adjacent to the first scanning line. The period when the polarity of the voltage applied to each pixel electrode corresponding to the second scanning line selected after the first scanning line is the same as the period of the opposite polarity is longer. Liquid crystal display device. 2. The liquid crystal display device according to claim 1, wherein scanning lines corresponding to an upper end and a lower end of the positive and negative regions move downward for each selection period of the scanning lines. 3. The liquid crystal display according to claim 2, wherein when the scanning lines included in the positive polarity region and the negative polarity region are selected, a scanning line located at an upper end of the region is selected. apparatus. A plurality of scan lines and source lines;
A plurality of pixel electrodes provided corresponding to the intersection of the scanning line and the source line;
A common electrode facing the plurality of pixel electrodes;
A transistor provided corresponding to each of the plurality of pixel electrodes and turned on between the source line and the pixel electrode when the scanning line is selected;
A driving method for an active matrix liquid crystal display device comprising:
A positive polarity region in which the polarity of the voltage applied to the pixel electrode corresponding to a plurality of adjacent scanning lines within one frame period with respect to the potential of the common electrode is all positive,
The polarities of the voltages applied to the pixel electrodes that are not included in the positive polarity region , are adjacent to each other , and correspond to the same number of scanning lines as the scanning lines included in the positive polarity region are all negative. And a negative polarity region,
In one frame period, and select the scanning lines included in each of said positive polarity area and the negative region while skipping the scanning lines of a predetermined number are alternately one by one, to the selected scanning line By reversing the polarity of the voltage applied to the corresponding pixel electrode, select all of the plurality of scanning lines ,
Within the one frame period, the polarity of the voltage applied to each pixel electrode corresponding to an arbitrary first scanning line among the plurality of scanning lines with respect to the potential of the common electrode is adjacent to the first scanning line. The period when the polarity of the voltage applied to each pixel electrode corresponding to the second scanning line selected after the first scanning line is the same as the period of the opposite polarity is longer. For driving a liquid crystal display device. An electronic apparatus comprising the liquid crystal display device according to claim 1.

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