JPH11163877A - Two-way television receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a 2-way television receiver wherein information of a large capacity such as an application software or the like of a network interface unit(NIU) sent from a server storing the information is once stored in a 2nd memory in a set-top unit(STU), and wherein transfer path for transferring the information from the 2nd memory in the STU to a 1st memory in the NIU again is established to allow high speed transfer processing. SOLUTION: In this receiver, processing of information transfer from a 2nd memory 15 in an STU to a 1st memory 12 in an NIU is conducted via an ATM cell bus through an ATM cell/data conversion section 17 by using a simple and local ATM protocol inside an STB to transfer the information to the 1st memory 12 by a simple ATM data assembly procedure and stored therein. Thus, the data transfer processing is conducted and data with a large capacity are transferred at a high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an interactive television receiver capable of transferring data transmitted from a server to a set top unit to a network unit.

[0002]

2. Description of the Related Art FIG. 13 is a configuration diagram of a conventional interactive television network. More specifically, a server capable of transmitting and receiving stored information and a plurality of interactive television receiving apparatuses Set connected to the server. An example of an interactive television network configured between Top Boxes (hereinafter referred to as STBs) is shown. In the figure, 1 is a server that can transmit and receive, 2 to 5 are STB1 to STBn connected to the interactive television network, and n STBs are connected to one server. When information is exchanged between the server and the STB on the network, particularly when information is sent from the bidirectional server to the STB, it is hereinafter referred to as download from the server to the STB.

[0003] An international technical standard DAVIC (Digital-Audio-Video-I
nteractive-Council) describes the internal configuration of the STB as a network interface unit (Ne) which is an interface between the STB and an external interactive television network.
twork-Interface-Unit: NIU) and NI
The UU stipulates that it is divided into two units, a set-top-unit (hereinafter referred to as STU) for processing and storing the data input by the U. F to the ATM cell bus and I2
It is also stipulated that connection by C bus is required (collectively, A0
I / F). In the configuration called level B, data downloaded from the server to the STB is not directly stored in the memory of the NIU, but is always stored in the memory inside the STU. The transfer method is not specified.

FIG. 14 is a block diagram showing a conventional interactive television receiving apparatus, and is an example showing an internal configuration of a conventional STB of level B specified by the DAVIC. In the figure, 6 is NIU, 7 is STU, 8 is NIU
Connected directly to an external interactive television network at S
Network I to convert to signal form that can be processed in TB
A / F sections 9 are connected to the network I / F section 8 and the ATM cell bus, and extract and relay ATM cells.
The TM cell relay unit 10 is connected to the ATM cell bus,
A for assembling and disassembling ATM cells inside TU7
TM cell processing unit, 11 is a first microprocessor for controlling data transfer and the like inside the NIU, and 12 is a first microprocessor of 11
A first memory 13 connected to an external bus of the microprocessor of the first, a first I2C controller connected to an external bus of the microprocessor 11 and connected to the STU of 7 by an I2C bus, and 14 A second microprocessor for controlling data transfer and the like inside the STU,
15 is a second memory connected to the external bus of the 14 second microprocessor, 16 is connected to the external bus of the 14 second microprocessor, and 6 NIUs and I
2 shows a second I2C controller connected by a 2C bus. FIG. 9 is a diagram showing a logical format of an ATM cell, and FIG. 10A is a diagram showing a data assembling procedure performed by the ATM cell processing unit 10.

Next, the operation will be described. In FIG. 13, consider a case where data stored in the server is downloaded to the STB through the interactive television network. In FIG. 14, data input to the STB from the interactive television network is first transmitted to the NIU6.
Is converted into a signal form which is input to the network I / F unit 8 and processed in the STB. Then, the converted signal is input to the ATM cell relay section 9 at the subsequent stage, where the ATM cell is extracted. Here, the microprocessor 12 for controlling the data transfer inside the NIU is the AT 12 shown in FIG.
AT to be extracted in advance based on the logical format of M cells
It is necessary to set the VCI value of the M cell in the ATM cell relay unit 9 in advance. Next, the AT extracted by the ATM cell relay unit 9
The M cell is sent to the STU 7 through the ATM cell bus.

[0006] Inside the STU7, the ATM cell stores the above-mentioned AT.
It is sent to the ATM cell processing unit 10 connected to the M cell bus. The ATM cell processing unit 10 performs a complicated process as shown in FIG. 10A according to a normal ATM processing protocol. First, the ATM layer VCI of the ATM cell
Are classified by value, and SAR-
Assembled into PDU. Further, after performing complicated processing such as CRC check, PAD removal, and other processing of each parameter in the convergence sublayer, plane data is reassembled. The second microprocessor 14 transfers and stores the plane data extracted by the ATM cell processing unit 10 to the second memory 15 through the external bus of the second microprocessor 14.

[0007]

Since the conventional interactive television receiver is configured as described above, when downloading a large amount of data from the server to the STB,
In particular, when downloading a large amount of data of application software to the NIU, the STB does not have a path for directly storing data received from the network in the first memory inside the NIU, and the STB does not always have a path. It is stored in the second memory. Therefore, it becomes necessary to transfer data from the second memory inside the STU to the first memory inside the NIU.
The level B configuration defined by C does not define a path for transferring data from the second memory inside the STU to the first memory inside the NIU, and thus cannot transfer data from the NIU to the STU. There was a point.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems. When a large amount of application data needs to be downloaded from a server to an NIU, the data is transmitted from the server and sent to the STU. It is an object of the present invention to obtain an interactive television receiver which enables application data of the NIU stored in the second memory to be transferred to the first memory inside the NIU.

[0009]

In the interactive television receiver according to the present invention, a large amount of information such as NIU application software transmitted from a server storing the information is temporarily stored in the second STU. When stored in the memory and transferred to the first memory of the NIU again, the information is once converted into ATM cells, transmitted to the ATM cell / data conversion unit via the ATM cell bus, and a simple ATM data assembling procedure. Is converted from ATM cells into data, transferred to a first memory under the control of a first microprocessor, and stored.

In the NIU, the first memory may be a memory having two input / output ports.
A data transfer path from the cell / data converter to the first memory; a first microprocessor for transmitting information stored in the second memory of the STU to the first memory of the NIU; Using the dedicated path for data transfer from the ATM cell / data converter to the first memory without the intervention of the first
And stored in the memory.

Further, when the information stored in the second memory of the STU is transferred to the first memory of the NIU, the second
Data is transmitted by an I2C transfer procedure through an I2C controller and a first I2C controller via an I2C bus, and is controlled by a first microprocessor.
It is configured to be transferred to and stored in a first memory.

Also, the NIU receives the ST via the I2C bus.
A memory controller controlled by a second microprocessor of the U, and when information stored in the second memory of the STU is transferred to the first memory of the NIU, a memory address and a memory of a transfer destination by the memory controller. A control signal is output, and information is transferred and stored from the first I2C controller to the first memory without the intervention of the first microprocessor.

Further, the NIU has a parallel data receiver,
First selecting means for switching the path to the ATM cell bus to a path to a parallel data receiver and a path to an ATM cell relay unit; a parallel data transmitter to the STU; and a parallel data path to the ATM cell bus. A second selecting unit for switching between a path from the transmitter and a path from the ATM cell processing unit, wherein the information stored in the second memory of the STU is transferred to the first memory of the NIU. By switching between the first selecting means and the second selecting means, the data is transmitted in a simple data format through a parallel data transmitter, an ATM cell bus, and a parallel data receiver, and is controlled by the first microprocessor. It is configured to be transferred to and stored in a first memory.

In the NIU, the first memory may be a memory having two input / output ports, provided with a dedicated data transfer path from the parallel data receiver to the first memory, and provided with a second memory of the STU. Information stored in memory is N
When transferred to the first memory of the IU, the first data is transferred from the parallel data receiver to the first memory using the second dedicated data transfer path without the intervention of the first microprocessor.
And stored in the memory.

Further, a serial data receiver is provided to the NIU,
Third selecting means for switching the path to the I2C bus between the path to the serial data receiver and the path to the first I2C controller; and the STU to the serial data transmitter and the serial path to the I2C bus. A fourth selection unit for switching between a path from the data transmitter and a path from the second I2C controller, wherein information stored in the second memory of the STU is transferred to the first memory of the NIU. By switching between the third selection means and the fourth selection means, the data is transmitted in a simple data format through the serial data transmitter and the serial data receiver, and the I2C bus, and is transmitted to the first microprocessor. And transferred to and stored in the first memory.

In the NIU, the first memory may be a memory having two input / output ports, provided with a third data transfer dedicated path from the serial data receiver to the first memory, and A third data transfer from the first serial data receiver to the first memory without the intervention of the first microprocessor, when the information stored in the second memory is transferred to the first memory of the NIU; It is configured to be transferred to and stored in the first memory using a dedicated path.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 FIG. 1 is a block diagram showing an interactive television receiver according to Embodiment 1 of the present invention. In the figure, 6 is an NIU which is an interface between the STB and the external interactive television network, 7 is an STU which processes and stores data from the network inputted by the NIU, and 8 is a direct connection to the external interactive television network in the NIU. A network I / F unit 9 for converting a signal on the interactive television network into a signal form that can be processed in the STB is connected to the network I / F unit 8 and an ATM cell bus to extract and relay ATM cells. An ATM cell processing unit connected to an ATM cell bus for assembling and disassembling ATM cells inside the STU 7, and a first unit 11 for controlling data transfer inside the NIU.
Microprocessor 12 and microprocessor 11
The first memory 13 connected to the external bus of the microprocessor 11 is connected to the external bus of the microprocessor 11 and the STU 7
A first I2C controller connected with the I2C bus,
Reference numeral 14 denotes a second microprocessor for controlling data transfer and the like inside the STU, 15 denotes a second memory connected to an external bus of the second microprocessor, and 16 denotes one memory.
A second IU connected to the external bus of the second microprocessor and to the NIU of 6 and the I2C bus.
2C controller, 17 is connected to the ATM cell bus,
1 shows an ATM cell / data conversion unit for converting an ATM cell into data by a simple ATM data assembling procedure. As described above, the STB is roughly divided into two blocks, the NIU 6 and the STU 7. FIG. 10B
FIG. 4 is a diagram showing a simple ATM data assembling procedure performed by the ATM cell / data converter 17;

Next, the operation will be described. In FIG. 13, consider a case where data stored in the server, particularly application software data required for the NIU, is downloaded to the STB via the interactive television network. In FIG. 1, data input to the STB from the interactive television network is first transmitted to the NIU.
6 is converted into a signal form which is input to the network I / F section 8 and processed in the STB. Then, the converted signal is input to the ATM cell relay section 9 at the subsequent stage, where the ATM cell is extracted. Here, the first microprocessor 11 which controls the data transfer inside the NIU sets the VCI value of the ATM cell to be extracted in advance in the ATM cell relay unit 9 based on the logical format of the ATM cell shown in FIG. Need to be kept. Next, the ATM cells extracted by the ATM cell relay unit 9 are sent to the STU 7 through the ATM cell bus.

Inside the STU 7, the ATM cell stores the above-mentioned AT.
The data is sent to the ATM cell processing unit 10 connected to the M cell bus, and the processing shown in FIG. 10A is performed. First, the ATM layer classifies the ATM cells according to their VCI values, and the cell assembly / division layer assembles them into SAR-PDUs. The convergence sublayer performs complicated processing such as CRC check, PAD removal, and processing of each parameter. After that, the necessary data is reassembled. The second microprocessor 13 transfers the data extracted by the ATM cell processing unit 10 into the second memory 14 through the external bus of the second microprocessor 13, classifies the data, and temporarily stores the data. Next, the NIU application software data stored in the second memory 14 is again transferred to the A via the external bus of the second microprocessor 13.
The ATM cell is transferred to the TM cell processing unit 10, packed in ATM cells, and added with a local VCI value inside the STB other than the VCI value used between the server and the STB.
It is sent to the cell bus. On the other hand, in the NIU, the ATM cell / data converter 17 connected to the ATM cell bus performs special processing as shown in FIG. 10B, which is simpler than a normal ATM protocol. First, in the ATM layer, A to which a specific VCI value sent from the STU is added.
Detect TM cell and SAR in cell assembly / division layer
After assembling into PDUs and further performing only simple processing such as PAD removal in the convergence sublayer, plane data is assembled. NI assembled
The U application software data is transferred to the first memory 12 by the first microprocessor 11 and stored therein.

Since the interactive television receiver according to the first embodiment is configured as described above, the application software data of the NIU stored in the STU is transmitted through the ATM cell bus and locally in the STB. STU to N using simple ATM data assembly procedure
Enabled to transfer to IU.

Embodiment 2 FIG. FIG. 2 is a block diagram showing an interactive television receiver according to Embodiment 2 of the present invention. In the figure, 1 to 17 have the same configuration as that of the first embodiment, and a description thereof will be omitted. 18 is an ATM cell /
This is a first data transfer dedicated path for transferring output data from the data conversion unit to the first memory 12 having two input / output ports without passing through the first microprocessor 11.

Next, the operation will be described. Embodiment 1
In FIG. 2, the NIU application software data reassembled by the ATM cell / data converter 17 is transferred and stored in the first memory 12 by the first microprocessor 11. In this manner, the data is transferred using the dedicated data transfer path 18 so that the data is transferred and stored in the first memory 12 having two input / output ports without passing through the first microprocessor 11. The same operation can be performed by such a configuration, and a transfer process can be performed.

Embodiment 3 FIG. FIG. 3 is a block diagram showing an interactive television receiver according to Embodiment 3 of the present invention. In the figure, 1 to 16 have the same configuration as that of the first embodiment, and the description is omitted. FIG. 11 shows I2
FIG. 9 is a diagram illustrating a procedure of C bus data transfer.

Next, the operation will be described. Embodiment 1
In FIG. 2, the NIU application software data stored in the second memory 15 is transferred to the ATM cell processing unit 10 again, packed again in the ATM cell, and transmitted to the NIU through the ATM cell bus. The NI stored in the second memory 15 as shown in FIG.
The application software data of U is sent to the second I2C controller 16 through the external bus of the second microprocessor 14, and is sent to the NIU 6 as serial data through the I2C bus. The procedure at this time is as follows:
The I2C controller 16 issues a start condition on the I2C bus and performs bus arbitration. Second I
When recognizing that the 2C controller 16 has become the bus master, the 2C controller 16 outputs the address of the first I2C controller 13 onto the I2C bus and signals data transmission. In response to this, the first I2C controller 16 returns a confirmation signal to the second I2C controller 16 when the preparation for data reception is completed. Next, the second I2C controller 16 that has received the confirmation signal starts transmitting data required by the NIU 6. The second I2C controller 16 waits for the completion of transmission for each 1-byte transmission and for a reception confirmation signal from the first I2C controller 13. The first I2C controller 13 returns a reception confirmation signal to the second I2C controller 16 every time one byte is received.
Thereafter, all data is transmitted by repeating the 1-byte data transfer and the reception confirmation signal. In the NIU 6, the application software data received in the above-described procedure from the first I2C controller 13 connected to the I2C bus is stored in the first memory 12 connected to the external bus by the first microprocessor 11. Transfer to and store. With such a configuration, a similar operation can be performed, and a transfer process can be performed.

Embodiment 4 FIG. 4 is a block diagram showing an interactive television receiver according to Embodiment 4 of the present invention. In the figure, the configuration from 1 to 16 is the same as that of the third embodiment, and the description is omitted. A memory controller 19 is controlled by the second microprocessor via the I2C bus, and transfers output data from the first I2C controller 13 to the first memory 12 without passing through the first microprocessor 11. It is.

Next, the operation will be described. Embodiment 3
Now, the NI output from the first I2C controller 13
Although the application software data of U is configured to be transferred and stored in the first memory 12 by the first microprocessor 11, in the present embodiment, the data is transferred using the memory controller 19 as shown in FIG. . In this procedure, first, the second I2C controller 16 issues a start condition on the I2C bus and performs bus arbitration. Upon recognizing that the second I2C controller 16 has become the bus master, the second I2C controller 16 outputs the address of the memory controller 19 and signals the data transmission. In response to this, the memory controller 19 prepares the second I2C controller 1 when data is ready to be received.
A confirmation signal is returned to 6. Next, the second I2C controller 16 that has received the confirmation signal transmits the address of the first memory 12 where the application software data is to be stored. The transmitted address is the memory controller 19
Is stored in Next, the second I2C controller 16 outputs the address of the first I2C controller 13 onto the I2C bus and signals data transmission. First I2
In response to this, the C controller 13 returns a confirmation signal to the second I2C controller 16 when the preparation for data reception is completed. Next, the second I2 receiving the confirmation signal
The C controller 16 starts transmitting data required by the NIU. The second I2C controller 16 is 1 byte
It waits for the completion of transmission and a reception confirmation signal from the first I2C controller 13 for each transmission. In NIU6, the first I
The 2C controller 13 activates the memory controller 19 every time one byte of data is received, and transfers data to the address of the first memory 12 stored in the memory controller 19 without passing through the first microprocessor 11. After the transfer is completed, the address stored in the memory controller 19 is automatically incremented. When the transfer is completed, a reception confirmation signal is returned to the second I2C controller 16. Hereinafter, all data are transmitted by repeating 1-byte data transfer, transfer by the memory controller 19, and a reception confirmation signal. As described above, in the NIU 6, the data is transferred and stored in the first memory 12 by the memory controller 19 without passing through the first microprocessor 11. With such a configuration, a similar operation can be performed, and a transfer process can be performed.

Embodiment 5 FIG. FIG. 5 is a block diagram showing an interactive television receiver according to Embodiment 5 of the present invention. The configuration up to the second I2C controller 16 is the same as that of the first embodiment, and a description thereof will be omitted. In the figure, 2
0 is a parallel data receiver connected to the external bus of the first microprocessor 11, 21 is first selection means for switching the path from the ATM cell bus to the ATM cell relay unit 9 or the parallel data receiver 20, Reference numeral 22 denotes a parallel data transmitter connected to the external bus of the second microprocessor 14, and 23 denotes a path to the ATM cell bus by the ATM cell processing unit 10 or the parallel data transmitter 22.
This is a second selection means for switching to. FIG. 12 is a diagram showing a simple data format (used for parallel data transfer).

Next, the operation will be described. In FIG. 5, the NIU application software data stored in the second memory 15 is sent to the parallel data transmitter 22 through the external bus of the second microprocessor 14,
It is converted into a parallel data format of a simple format of only length information and data as shown in FIG. Then, the output from the parallel data transmitter 22 is selected by the second selecting means 23, and the converted parallel data is output on the ATM cell bus. On the other hand, in the NIU, the first selecting means 21 selects an input path to the parallel data receiver 20, and data on the ATM cell bus is input to the parallel data receiver 20. The data extracted here is transferred and stored in the first memory 12 by the first microprocessor 11.

Since the interactive television receiver according to the fifth embodiment is configured as described above, the application software data of the NIU is transmitted to the STU through the ATM cell bus and using a simple data format. To transfer data to NIU.

Embodiment 6 FIG. FIG. 6 is a block diagram showing an interactive television receiver according to Embodiment 6 of the present invention. In the figure, the components 1 to 23 are the same as those of the fifth embodiment, and the description is omitted. Reference numeral 24 denotes a second data transfer dedicated path for transferring output data from the parallel data receiver to the first memory 12 having two input / output ports without passing through the first microprocessor 11. FIG. 12 is a diagram showing a simple data format (used for parallel data transfer).

Next, the operation will be described. Embodiment 5
In the NI received by the parallel data receiver 20,
The application software data of U is configured to be transferred and stored in the first memory 12 by the first microprocessor 11, but is transferred using the second dedicated data transfer path 24 as shown in FIG. Thus, the configuration may be such that the data is transferred and stored in the first memory 12 having two input / output ports without passing through the first microprocessor 11, and the same operation can be performed by such a configuration. Can be performed, and the transfer process can be performed.

Embodiment 7 FIG. 7 is a block diagram showing an interactive television receiver according to Embodiment 7 of the present invention. The description up to the second I2C controller 16 is omitted since it is the same as that of the third embodiment. In the figure, 2
5 is a serial data receiver connected to the external bus of the first microprocessor 11, 26 is a third selection means for switching the path from the I2C bus to the first I2C controller 13 or the serial data receiver 25 , 2
7 is a serial data transmitter connected to the external bus of the second microprocessor 14, and 28 is fourth selecting means for switching the path to the I2C bus to the second I2C controller 16 or the serial data transmitter 28. It is. FIG. 12 is a diagram showing a simple data format (used for serial data transfer).

Next, the operation will be described. In FIG. 7, the NIU application software data stored in the second memory 15 is sent to the serial data transmitter 27 through the external bus of the second microprocessor 14,
It is converted into a serial data format of a simple data format of only length information and data as shown in FIG. The output from the serial data transmitter 27 is selected by the fourth selecting means 28, and the converted serial data is output on the I2C bus. On the other hand, in the NIU, the third selection means 26 selects an input path to the serial data receiver 25, and data on the I2C bus is input to the serial data receiver 25. The data extracted here is transferred and stored in the first memory 12 by the first microprocessor 11.

Since the interactive television receiver according to the seventh embodiment is configured as described above, the application software data of the NIU is transmitted through the I2C bus.
In addition, it is possible to transfer data from the STU to the NIU by using a serial data format having a simple data format.

Embodiment 8 FIG. FIG. 8 is a block diagram showing an interactive television receiver according to Embodiment 8 of the present invention. In the figure, the configuration from 1 to 28 is the same as that of the seventh embodiment, and the description is omitted. Reference numeral 29 denotes a third data transfer dedicated path for transferring output data from the serial data receiver to the first memory 12 having two input / output ports without passing through the first microprocessor 11. FIG. 12 is a diagram showing a simple data format (used for serial data transfer).

Next, the operation will be described. Embodiment 7
In the NI received by the serial data receiver 25,
The application software data of U is configured to be transferred and stored in the first memory 12 by the first microprocessor 11, but is transferred by using the third data transfer path 29 as shown in FIG. Thus, the configuration may be such that the data is transferred and stored in the first memory 12 having two input / output ports without passing through the first microprocessor 11, and the same operation can be performed by such a configuration. Can be performed, and the transfer process can be performed.

[0037]

Since the present invention is configured as described above, it has the following effects.

In the interactive television receiver according to the present invention, the transfer processing when transferring data from the second memory inside the STU to the first memory inside the NIU is performed by the NI.
ATM cell / data converter provided inside U, and ATM
Since the data transfer is performed using the cell bus and the ATM data assembling procedure of the local simple protocol inside the STB, data transfer processing can be performed, and large-capacity data can be transferred at high speed.

Further, the ATM cell /
A first data transfer dedicated path for performing data transfer from a data converter, an ATM cell bus, and an ATM cell / data converter to a first memory having two input / output ports without the intervention of a first microprocessor. Is used, the data transfer process can be performed, the transfer process can be performed at a higher speed, and the load on the first microprocessor can be reduced.

Further, the first I2C controller inside the NIU, the second I2C controller inside the STU, and the I2C bus connecting the first I2C controller and the second I2C controller are used, and the I2C transfer procedure is used. Therefore, data transfer processing can be performed.

Further, a first I2C provided inside the NIU
A second I2C controller provided inside the controller and the STU, and a first I2C controller and a second I2C
The I2C bus connecting the C controller, and the memory controller controlled by the second microprocessor via the I2C bus. Since the I2C bus data transfer procedure is used, data transfer processing can be performed without the intervention of the first microprocessor. And the burden on the first microprocessor can be reduced.

A parallel data receiver provided inside the NIU, first selecting means for switching the ATM cell bus path, and a parallel data transmitter provided inside the STU;
By using the second selecting means for switching the path of the ATM cell bus and using a parallel data format having a simple data format, the transfer process can be performed, and the transfer process can be performed at a higher speed.

A parallel data receiver provided inside the NIU, first selecting means for switching the path of the ATM cell bus, and a parallel data transmitter provided inside the STU;
The parallel data having a simple data format is transmitted on the ATM cell bus using the second selecting means for switching the path of the ATM cell bus, and the first data is transmitted from the parallel data receiver to the first memory having two input / output ports. By using the second data transfer dedicated path for performing data transfer without the intervention of the microprocessor, the data transfer process can be performed, the transfer process can be performed at a higher speed, and the load on the microprocessor can be reduced.

Further, a serial data receiver provided inside the NIU, third selecting means for switching the path of the I2C bus, a serial data transmitter provided inside the STU,
The transfer processing can be made possible by using the fourth selecting means for switching the path of the 2C bus and by using a serial data format having a simple data format.

Also, a serial data receiver provided inside the NIU, third selecting means for switching the path of the I2C bus, a serial data transmitter provided inside the STU,
A first microprocessor which uses a serial data format having a simple data format by using a fourth selecting means for switching a path of the 2C bus, and from a serial data receiver to a first memory having two input / output ports. By using the third dedicated data transfer path for performing data transfer without intervention, the transfer processing can be performed and the load on the microprocessor can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an interactive television receiver according to Embodiment 1 of the present invention.

FIG. 2 is a block diagram illustrating an interactive television receiver according to a second embodiment of the present invention.

FIG. 3 is a block diagram illustrating an interactive television receiver according to a third embodiment of the present invention.

FIG. 4 is a block diagram illustrating an interactive television receiver according to a fourth embodiment of the present invention.

FIG. 5 is a block diagram illustrating an interactive television receiver according to a fifth embodiment of the present invention.

FIG. 6 is a block diagram illustrating an interactive television receiver according to a sixth embodiment of the present invention.

FIG. 7 is a block diagram illustrating an interactive television receiver according to a seventh embodiment of the present invention.

FIG. 8 is a block diagram illustrating an interactive television receiver according to an eighth embodiment of the present invention.

FIG. 9 is a diagram showing a logical format of an ATM cell.

FIG. 10 is a diagram showing an ATM data assembling procedure.

FIG. 11 is a diagram showing an I2C bus data transfer procedure.

FIG. 12 is a diagram showing a simple data format used in the present invention.

FIG. 13 is a configuration diagram of a conventional interactive television network.

FIG. 14 is a block diagram showing a conventional interactive television receiver.

[Description of Signs] 1 interactive server, 2 to 5 interactive television receiving terminals (STB) 1 to n, 6 network interface unit (NIU), 7 set top unit (S
TU), 8 network I / F section, 9 ATM cell relay section, 10 ATM cell processing section, 11 first microprocessor, 12 first memory, 13 first I2C controller, 14 second microprocessor, 15
Second memory, 16 second I2C controller, 17
ATM cell / data converter, 18 first data transfer dedicated path, 19 memory controller, 20 parallel data receiver, 21 first selection means, 22 parallel data transmitter, 23 second selection means, 24 second Dedicated path for data transfer, 25 serial data receiver, 26
Third selecting means, 27 serial data transmitter, 28
Fourth selecting means, 29 Third dedicated route for data transfer.

Claims (8)

[Claims] An interactive television network in which a path for mutually communicating information is established between a server storing information and a plurality of interactive television receiving terminals (STBs) connected to the server. I / F unit connected to a television network, A
TM cell relay unit, ATM cell / data conversion unit, and first
, A first I2C controller, a network interface unit (NIU) including a first microprocessor that controls them, an ATM cell processing unit, and a second memory, a second I2C controller, which controls them A set top unit (STU) having a second microprocessor, and an ATM cell bus and an ITU between the two units.
A two-way television receiver connected via a 2C bus, and large-capacity information such as application software of the network interface unit transmitted from a server storing the information is temporarily stored in a second memory in the set-top unit. 2 is stored in the second memory and transferred to the first memory in the network interface unit again.
The data is transmitted to the ATM cell / data conversion unit via the ATM cell bus, and is transmitted to the ATM in a simple ATM data assembling procedure.
An interactive television receiver, wherein the data is converted from M cells into data, transferred to a first memory under the control of a first microprocessor, and stored. 2. The network interface unit according to claim 1, wherein the first memory is a memory having two input / output ports, and a dedicated data transfer path from the ATM cell / data converter to the first memory is provided. And information stored in a second memory in the set top unit is stored in a first memory in the network interface unit.
When the data is transferred to the first memory, the data is transferred to the first memory from the ATM cell / data conversion unit to the first memory using the dedicated data transfer path without the intervention of the first microprocessor, and stored. The interactive television receiver according to claim 1, wherein: 3. When information stored in a second memory in the set top unit is transferred to a first memory in the network interface unit, the information is transferred via the second I2C controller and the I2C bus. 2. The bidirectional communication system according to claim 1, wherein data is transmitted in an I2C transfer procedure through a first I2C controller, transferred to a first memory under the control of a first microprocessor, and stored. Television receiver. 4. A network controller in the network interface unit, the memory controller being controlled by a second microprocessor in the set top unit via the I2C bus, wherein a second memory in the set top unit is provided. When the stored information is transferred to a first memory in the network interface unit, a memory address and a memory control signal of a transfer destination are output by the memory controller, and the first memory is output without a first microprocessor. 4. The interactive television receiver according to claim 1, wherein information is transferred from the I2C controller to the first memory and stored. 5. A parallel data receiver in the network interface unit, and first selecting means for switching a path to the ATM cell bus between a path to the parallel data receiver and a path to the ATM cell relay unit. A parallel data transmitter in the set-top unit, and a second selector for switching a path to the ATM cell bus between a path from the parallel data transmitter and a path from the ATM cell processing unit. When the information stored in the second memory in the set top unit is transferred to the first memory in the network interface unit, by switching between the first selecting means and the second selecting means Through the parallel data transmitter and ATM cell bus, and through the parallel data receiver 2. The interactive television receiver according to claim 1, wherein the data is transmitted in a simple parallel data format, controlled by a first microprocessor, transferred to a first memory and stored. . 6. In the network interface unit, the first memory may be a memory having two input / output ports, and has a dedicated data transfer path from the parallel data receiver to the first memory. When the information stored in the second memory in the set top unit is transferred to the first memory in the network interface unit, the first data is transferred from the parallel data receiver to the first memory without the intervention of the first microprocessor. 2. The data is transferred to the first memory and stored in the first memory using the second data transfer path.
Or the interactive television receiver according to claim 5. 7. A serial data receiver in the network interface unit, and a third selecting means for switching a path to the I2C bus between a path to the serial data receiver and a path to the first I2C controller. And a serial data transmitter in the set-top unit, and a path from the serial data transmitter to the I2C bus and the second I2C bus.
Fourth selection means for switching to a path from the controller, wherein the information stored in the second memory in the set top unit is transferred to the first memory in the network interface unit. 3
By switching between the selection means and the fourth selection means, the data is transmitted in a simple data format of serial data through the serial data transmitter, the serial data receiver, and the I2C bus, and is controlled by the first microprocessor. 7. The interactive television receiving apparatus according to claim 1, wherein the information is transferred to the first memory and stored. 8. In the network interface unit, the first memory may be a memory having two input / output ports, and a third dedicated data transfer path from the serial data receiver to the first memory. Wherein when the information stored in the second memory in the set top unit is transferred to the first memory in the network interface unit, the first serial data is transmitted without the intervention of the first microprocessor. The interactive television receiver according to claim 1 or 7, wherein the data is transferred from the data receiver to the first memory to the first memory using a third data transfer path, and is stored. apparatus.