JPS6040748B2 - Packet switching method in packet switching network - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a packet-switched method in a packet-switched network, and in particular to a packet-switched system with additional functions in order to accommodate data transmission equipment having an interface to a circuit-switched network within the packet-switched network. The present invention relates to a packet switching method performed between mSEs in a packet switching network equipped with switching equipment (hereinafter abbreviated as IPSE).

The switching network for data transmission is the so-called circuit switching network (hereinafter referred to as CS).
(abbreviated as N) and packet switched networks (hereinafter abbreviated as PSN).

FIG. 1 is a block diagram showing an example of a conventional CSN exchange operation, and 1 indicates a CSN.

2a and 2b are circuit switching devices (hereinafter abbreviated as CSE), and CSE2a and CSE2b indicate that devices with the same structure are provided at different locations.

Throughout the following description, the same numerals refer to devices with the same structure; the suffix a indicates a device primarily described in relation to outgoing calls, and the suffix b indicates a device primarily described in connection with incoming calls. 3a and 3b are data transmission equipment (hereinafter abbreviated as CST) each having an interface to a circuit switched network.

When the CST 3a sends a calling signal, the CSE 2a receives it, exchanges control information between the CSEs, and
Instructs ST3b to receive a call.

When CST3b accepts an incoming call, it sends out an acceptance signal and sends a CSN
A communicable signal from CST 3a is returned via I. These are 50, 51, and 52 shown in FIG. 1, and when this procedure is completed, a communication path 53 between CST 3a and CST 3b is set. After that, using this communication path 53, CST3a and CS
Data transmission between T3b is performed, but data is not stored within the CSNI, so no data transfer delay occurs (hereinafter such data taken by the CST will be referred to as synchronous data). After the data transmission is completed, the communication path is disconnected as shown at 54, 55, and 56 in FIG. 1 in the same sequence as the connection procedure. Figure 2 shows the conventional PSN
4 is a block diagram showing an example of an exchange operation, and 4 indicates a PSN.

5a and 5b are packet switching devices (hereinafter abbreviated as PSE), and 6a and 6b are data transmission devices (hereinafter referred to as PS) each having an interface to a packet switching network.
(abbreviated as T).

Message data sent from the PST 6a to the inner N4 is decomposed into packets 57, stored and exchanged in each PSE in the inner N4, and transmitted to the terminating PST 6b. Within target N4, each packet does not pass through the same route, but depending on the processing load of each PSE or the state of the line within PSN4, the transfer time is the shortest.
It is controlled so that it follows the route that follows. This situation is indicated at 58 in FIG. In conventional data communication systems, the CSNI and the N4 form mutually independent switching networks, and therefore, the computer or terminal equipment that is data transmission equipment is connected to the CSNI as a CST, or is connected to the N4 as a PST. There was no switching network that could connect the CST and PST in the same way and transmit data between them. However, considering the economic efficiency of constructing and maintaining a switching network, there is a need for a switching network that can connect CST and $T in the same way. An invention filed separately by the applicant of the present application (hereinafter referred to as a separate application) discloses a packet switching processing device mSE that enables a connection between a PST and a CST in an N4. FIG. 3 is a block diagram showing an example of the configuration of a packet switching network using 1E. The same symbols as in FIGS. 1 and 2 indicate the same or corresponding parts, and 7 converts audio into a digital signal. 8 is a device (hereinafter abbreviated as A/D) that converts audio represented by a digital signal into an analog audio signal (hereinafter referred to as D/A).
), ga, and gb are each $1E.

The packet string 57 sent from PST6a is IPSE9a
and undergoes normal packet switching processing within PSN 4 as described with respect to FIG.

Also, the continuous bit string from CST3a and A/D7 is
The packets are blocked and added to the packets, and transferred in the form of packets within the PSN 4 to reach the terminating IPSE 9b. , CST3b, D/A8 or continuous bit string (
59) in FIG. 3 and transmits it. PSN as mentioned above
Transfer within PSN 4 is performed in the form of packet 58 and undergoes store-and-forward processing, resulting in a delay due to transfer within PSN 4.
Moreover, since there are variations in the delay time, E9b
It is necessary to absorb this variation. FIG. 4 is a block diagram showing an example of a storage device for converting a packet into a continuous bit string in the first gate E9b;
The same reference numerals as in the figure indicate the same parts, and 10 is a storage device. In FIG. 3, in order for the CST 3a to transmit a continuous bit string 59 to the IPSE 9a, and for the IPSE 9b to transmit the continuous bit string 59 to the CST 3b, the transfer speed of the packet 58 within the PSNI must be faster than the transmission speed of the continuous bit string 59. No. That is, the storage device 10
The packet 57 must be input into the storage device 10 before its stored contents can be retrieved as a continuous bit string 59. Therefore, the storage capacity required for the storage device is determined from the characteristics of the PSN 4, that is, the transfer delay time and its dispersion occurring within the silk, and the relationship between the transmission speed to the CST 3b and the transmission speed within the silk. What has been described above with respect to FIGS. 3 and 4 is an outline of the press SE disclosed in a separate application. By the way, in the configuration of the duck N4 shown in FIG. 3, it is necessary to make the transfer delay time of the packet 58 within the duck N4 as small as possible, and to make the variation in the transfer delay time as small as possible.
This is because if the variation in transfer delay time increases, the capacity of the storage device 10 must be increased accordingly to ensure continuity of bits from E9b to CST3b.
Fig. 5 is a timing diagram showing an example of the timing of packet transfer in order to minimize the intra-network transfer delay time and reduce fluctuations in the conventional whistle N, and Fig. 5a shows a frame of fixed time mf. A method is shown in which each frame is divided into time slots corresponding to the packet length, each packet reserves one time slot, and the data transfer period exclusively uses this reserved time slot.

In Fig. 5b, time slots configured in the same manner as in Fig. 5a are reserved, but the slot interval can be set arbitrarily (in the figure, T
, and T2) show the methods that can be set. Figure 5a
, b, one time slot is one time slot.
Since the time slot is occupied by one packet and cannot be used for anything else even when that packet is not being transferred, the efficiency on the transfer path is low. In particular, the method shown in Figure 5 a is able to transfer even packets with a large chance of being transferred. The efficiency on the transmission path further decreases in that packets with small opportunities also have similar slot intervals. Now, Fig. 5 shows the conventional method of packet transfer control within the HakuN4 shown in Fig. 2.
It can be used to control the transfer of packets within the PSN 4 shown in FIG.

In other words, the data transmitted in the continuous bit string 59 is called sardine data, and the packet of synchronous data is called a synchronous data packet, and the time slots shaded in FIG. 5 are the times reserved for the synchronous data packet. slots (in the following drawings, the shaded time slots are also time slots for synchronous data packets), the method of FIG. 5 can be used for I N4 of FIG. 3. However, as mentioned earlier, Figure 5a
, b have the drawback of low efficiency on the transfer path. In addition, in FIG. 5c, long and short packets are not classified, and the timing control section 32 sends the synchronous data packet at a timing T.
syn, and if no other packets have been sent at the time Tsyn is output, it will immediately send a synchronous data packet, and if another packet has already been sent at this point, the synchronous data will be sent at the end of the other packet. Send a packet.
Therefore, since the method shown in FIG. 5c can make the packet length variable, the efficiency on the transfer path is improved compared to the methods shown in FIGS. 5a and b, but as shown in FIG. T
,, ΔT2, and the disadvantage is that the storage device lo (see FIG. 4) must have extra capacity to absorb this fluctuation. The purpose of this invention is to eliminate the above-mentioned drawbacks in conventional packet switching methods, and to reduce the transfer delay time of synchronous data within a PSN with mSE, and to reduce the fluctuation of the transfer delay time by 4. The present invention aims to provide a packet switching method that can reduce the required capacity of a single storage device.

FIG. 6 is a block diagram showing an embodiment of the IME used in the present invention.
are buffer memories, 13, 21, and 26 are packet type determination units, respectively, 17 is a control packet processing unit, 18 is an asynchronous data packet processing unit, 19 is an exchange processing unit, 22 is an interface control unit, 23 is a buffer memory, and 24 is a Transmission control unit, 27 is a packet length determination unit, 28, 29, 30
3 is a sending matrix, 31 is a data transfer control unit, and 3 is a transmission holding matrix.
2 is a timing control unit, and 33 is a line connecting SE and the next stage 1E in this drawing.

Packets arriving from circuit 11 are stored in temporary buffer memory 1
2, and the packet type determination unit 13 determines whether it is a control packet 14, a data packet (hereinafter referred to as a synchronous data packet) 15 sent from the PST (see FIG. 3, 6a), or a synchronous data packet 16. The control packet 14 is processed by the control packet processing unit 17, and the asynchronous data packet 15 is processed by the asynchronous data packet processing unit.
6 and undergoes transfer route control in the exchange processing unit 19. If the packet is addressed to the data transmission equipment connected to the IPSE shown in this figure, it is output to the path 20' and the packet type is determined by the packet type determining unit 21. If it is an asynchronous data packet, it is sent to the PST ( If it is a synchronous data packet (see FIG. 3, 6b), it is once stored in the buffer memory 23, and then sent by the transfer control unit 24 to the CST, etc. (see CST3b, D/A8, FIG. 3). The packet relayed to the next stage IPSE is route 25
Accordingly, if the packet enters the packet type determining unit 26 and is an asynchronous data packet, it is input to the packet length determining unit 27, where it is divided into long packets and short packets and placed in respective transmission queues 28 and 29.

A packet determined to be a synchronous data packet by the packet type determining unit 26 is inputted to the sending matrix 30'. The packets in each of the transmission queues 28, 29, and 301 are transmitted from the packet transfer control section 31 to the line 33 at timings controlled by the timing control section 32.

FIG. 6 shows an example of a separately filed packet switching processing device. As shown in FIG. , 30, making it easy to control the transmission.

FIG. 7 is a timing diagram showing an embodiment of the present invention.
A timing having a period of s starvation (this timing is referred to as T2
), the timings T, , T having the same period before and after
3, the period of LT is set as state ST1, T, the period of -L is set as state ST2, the period of T2-T3 is set as state ST3,
In each state, by giving priority to the transmission from each transmission matrix 25, 29, 30, S
This is to minimize the time during which other packets are being sent during the T3 state.

FIG. 8 is an explanatory diagram showing the state transition in FIG.
Letters and symbols that are the same as those in the diagram have the same meaning, and in state STI P
Short packets are sent out with a priority of I, and long packets are sent out with a priority of S2.

Furthermore, in state ST2, new transmission of long packets is prohibited, and only short packets are transmitted. Also state ST3
In this case, all new asynchronous data packets are prohibited from being sent, and synchronous data packets are sent. However, state ST3
However, the transmission of the packet that is already being transmitted continues as it is, and the synchronous data packet is transmitted after it is finished. If a plurality of synchronous data packets are reserved, the plurality of synchronous data packets are sent out in state ST3. 9th
The figure is a timing diagram showing a specific example of the control shown in FIG.
The figure shows an example in which the time in state ST3 is equal to the transmission time of one synchronous data packet.

In FIG. 9a, by further adding timing T*, a state of guard time period ST* is established, and this guard time period S
No new packets are sent within T*. In the example shown in FIG. 9a, the sending of long packets starts near the end of state STI.
This is completed near the end of T2, and at this point the sending of short packets begins, but this is completed within state ST*, indicating that only synchronous packets can always be sent in state ST3. Although the efficiency of the transmission path decreases due to the provision of the guard time period ST*, this guard time period ST
Since * is only a time corresponding to a short packet length, the above-mentioned decrease in efficiency is not large, and synchronous data packets have the advantage that there is no waiting for transfer, and variations in time delay due to this can be eliminated. In the specific examples shown in Figures 9b and 9c, there is no guard time period, so △ is added to these drawings.
Although this causes fluctuation in the delay time shown as T, control can be made that much simpler.

The method shown in FIG. 9b is to make the time of state ST2 the same as the transfer time of the maximum length packet, so that the delay time △T due to the completion of sending the short packet sent just before timing T2
is the maximum value of delay time fluctuation.

The method shown in FIG. 9c is an embodiment in which the time in state ST2 is made shorter than the transfer time of the maximum length packet to improve the efficiency on the transmission path, and in the example shown in FIG. , the short packet transfer time ts, and the time b in state ST2 with an interval t = b 10. In this case, as is clear from the figure, the delay time of the synchronous data packet is The maximum value of the fluctuation is the same as in the case of FIG. 9b.

Also, in Fig. 9c, if tso>(t2b+G), the maximum value of the fluctuation in the delay time of the synchronous data packet is the 9th
It is larger than the case in Figure b. The actual packet lengths in OreN are about 128 to 250 bytes for the maximum length packet, 16 bytes for the shortest packet, and 32 to 64 bytes for the synchronous data packet, so the method shown in FIG. 9b is difficult to control.
Considering the efficiency of the transmission line, this can be said to be the most suitable overall.

As described above, the present invention provides a method for implementing a packet switching network most economically when a packet switching device with additional functions is provided to accommodate data transmission equipment having an interface to a circuit switching network within the packet switching network. It provides a configurable exchange method.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an example of the switching operation of a subordinate CSN, Fig. 2 is a block diagram showing an example of the switching operation of a conventional PSN, and Fig. 3 is a block diagram showing an example of the switching operation of a conventional PSN. A block diagram showing an example, FIG. 4 is a block diagram showing an example of a storage device for converting packets into a continuous bit string in IPSE, and FIG. 5 is a timing diagram showing the timing of transfer of each packet in a conventional PSM. FIG. 6 is a block diagram showing an embodiment of IPSE used in this invention, FIG. 7 is a timing diagram showing an embodiment of this invention, and FIG. 8 is an explanatory diagram showing state transfer in FIG. 7. FIG. 9 is a timing diagram showing a specific example of the control shown in FIG. 7. In these figures, 1 is CSN (circuit switched network), 2a
, 2b are CSE (circuit switching equipment), 3a, 3b respectively
are respectively CST (data transmission equipment with an interface to CSN), and 4 is PSN (packet switching network).
, 5a and 5b are Kamo E (packet switching device) and 6, respectively.
a and 6b are respectively PST (data transmission equipment having an interface for PSN), 7 is D/A (device that converts audio into digital signals), and 8 is D/A (transferring audio represented by digital signals to analog audio signals). 10 is a storage device, 12 and 33 are lines, 12 and 23 are buffer memories, respectively.
3, 21, and 26 are respectively packet type determination units, 14 is a control packet, 15 is an asynchronous data packet, 16 is a synchronous data packet, 17 is a control packet processing unit, 18 is an asynchronous data packet processing unit, 19 is an exchange processing unit, 22
24 is an interface control unit, 24 is a transmission control unit, 27 is a packet determination unit, 28, 29, and 3 rivers have a transmission matrix, 31 is a packet transfer control unit, 32 is a timing control unit, 50, 51, and 52 are CSWs. Line connection procedure
53 is a communication path, 54, 55, 56 are line disconnections, 5
7 is a packet, 58 is a packet transfer route, and 59 is a synchronous data bit string. Note that the same reference numerals in each figure indicate the same or equivalent parts. Figure 4 Figure 2 Figure 3 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9

Claims (1)

[Scope of Claims] 1. Control packets and synchronous data packets obtained by packetizing digital signals transmitted from a data transmission device having an interface to a circuit-switched network, and control transmitted from a data transmission device having an interface to a packet-switched network. In the step of transferring the packet and the asynchronous data packet to a predetermined switching device in the packet switching network, the transferred packet is differentiated into a control packet, an asynchronous data packet, and a synchronous data packet, and the control packet is processed by the control packet processing unit and then converted into an asynchronous data packet. The packets are processed by the asynchronous data packet processing unit and the synchronous data packets are inputted as they are to the switching processing unit.The switching processing unit classifies the packets that are determined to be packets to be transferred to a switching device other than the relevant switching device according to the packet type. Then, the asynchronous data packets are further classified according to their packet lengths and added to their respective transmission queues, and the packets in the respective transmission queues are transferred to lines within the packet switching network according to the control timing from the timing controller. 1. A packet switching network method in a packet switching network, characterized by comprising a step of transferring. 2. The step of transferring the packets in each transmission queue to the lines in the packet switching network according to the control timing from the timing control unit is to a step of transmitting short packet length packets and long packet length packets in the first state with predetermined priorities, and a step of transmitting short packet length packets in the second state. 2. The method for switching packets in a packet switching network according to claim 1, further comprising the steps of transferring the synchronized packet, and transferring the synchronous packet in the third state. 3. The step of transferring the packets in each transmission queue to the line in the packet switching network according to the control timing from the timing control unit is performed by a predetermined time interval between the second state and the third state. A packet switching method in a packet switching network according to claim 2, characterized in that the method includes a guard time period. 4 The step of transferring the packets in each transmission queue to the line in the packet switching network according to the control timing from the timing control unit is to transfer other packets to the line in the packet switching network in accordance with the control timing from the timing control unit. 3. The packet switching method in a packet switching network according to claim 2, further comprising the step of transmitting the synchronous data packet immediately after the transfer is completed when the data is being transferred.