JP3120609B2 - Frame receiver - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame receiving apparatus, and more particularly to a frame receiving apparatus in a reception control device of a data communication system used for data transmission between home automation and audio-visual equipment in a home.

[0002]

2. Description of the Related Art For realizing home automation, various data communication systems using a bus which is a shared transmission line have been proposed and standardized. For example, D2B, a control bus used for data transmission between home audiovisual (AV) devices, standardized by the International Electrotechnical Commission (IEC), and standardized by the Japan Electronic Machinery Manufacturers Association and the Radio Technology Association There is a designated Home Bus System (HBS). These data communication systems transmit data in communication frames composed of packets in which addresses, control codes, and variable-length data are packaged.

Before describing a conventional frame receiving apparatus, the D2B system will be described as an example of a home data communication system.

FIG. 3 is a diagram showing a format of a communication frame of the D2B system. In FIG. 5, a communication frame FF includes a start bit S indicating the start of a frame,
A mode bit M specifying a communication mode, a master address field FM indicating the address of the transmission control device, a slave address field FS indicating the address of the reception control device, a control field FC indicating the type and transfer direction of communication data, And a data field FD on which communication data is mounted.

[0005] The maximum number of communication data that can be loaded in the data field FD is determined by the communication mode. For example, when the communication mode 2 is selected by the mode bit M, up to 128 bytes of communication data can be loaded in the data field FD. An acknowledge bit is added to each of the slave address field FS, the control field FC, and the data field FD,
When the reception control device receives the data normally, these acknowledge bits are returned to the transmission control device.

As shown in FIG. 2, the conventional frame receiving device 1 constitutes a reception control device for controlling reception of communication data of the D2B system together with the CPU 2. The frame receiving device 1 receives and stores communication data. CPU 2 reads the received data stored in frame receiving apparatus 1 and performs a predetermined process.

In FIG. 2, a conventional frame receiving apparatus 1
A receiving unit 11 that converts and demodulates a communication frame FF input from the bus into a logical signal and outputs a received signal RF;
Data link controller (hereinafter referred to as DLC) 1 for processing received signal RF based on a data link layer protocol
2 and a first-in first-out (hereinafter FIFO) storing received data RD (contents of data field FD) in received signal RF
The memory 13 includes a memory status unit 14 that indicates the status of the FIFO memory 13, and a reception status unit 15 that stores the status of the reception status output from the DLC 12.

[0008] The memory status section 14 supplies a status signal REP / RF to the DLC 12 indicating whether the FIFO memory 13 is empty (no stored data) or full with stored data.
L is output. Also, the status signal R is sent to the CPU 2.
Outputs EP.

Next, the operation of the conventional frame receiving apparatus will be described.

First, in the initial state, since the FIFO memory 13 is empty, the status signal REP becomes "1",
It is supplied to the DLC 12 and the CPU 2 respectively. Next, when the communication frame FF is transmitted to the bus, the DLC1
2 monitors the communication frame FF via the receiving unit 11. When it is confirmed that the communication frame FF is addressed to the own station, it is confirmed by the signal REP that the FIFO memory 13 is empty. As a result of this confirmation, the signal REP becomes '1'
That is, if the communication frame is empty, an acknowledgment signal is returned to the transmitting station, and reception of the communication frame FF is started.
The received data RD is stored in the FIFO memory 13 within a range where the FIFO memory is not full by monitoring the signal RFL. As a result of the above confirmation, if the signal REP is “0”, that is, not empty, the reception of the communication frame FF is rejected, and the receiving operation is terminated without returning an acknowledge signal to the transmitting station. The reason for this is that if the previous received data remains in the FIFO memory 13, it cannot be distinguished from the newly received data received this time. In this example, since the signal REP is “1”, the DLC 12 starts receiving the communication frame FF and stores the received data RD in the FIFO memory 13. When the reception is completed, a code indicating the end of the reception is set in the reception status section 15, and an interrupt is requested to the CPU 2.

In response to the interrupt request, the CPU 2 reads out the reception status section 15 and knows the end of reception. Next, the signal R
By reading the received data RD from the FIFO memory 13 until it becomes empty (cleared) while monitoring the EP, all the received data RD in the received communication frame FF can be taken out.

When the reception of the communication frame FF is terminated halfway and reading of the received data by the CPU 2 becomes unnecessary, the CPU 2 controls the FIFO memory 13 to clear it.

In the case of mode 2 in the above-described D2B system, the time from the end of the reception of 128 bytes of data to the start of the reception of the next communication frame is a minimum of about 2.2 ms. Therefore, in order to clear the FIFO memory 13, the CPU 2 needs to execute a 128-byte data reading process within 2.2 mS.

[0014]

In the above-described conventional frame receiving apparatus, the reception of the next communication frame cannot be started unless the FIFO memory is cleared. Therefore, the CPU performs a reading process for clearing the FIFO memory in a short time. It has to be executed, and there is a drawback that the processing of the CPU becomes a heavy burden.

[0015]

SUMMARY OF THE INVENTION A frame receiving apparatus according to the present invention constitutes a receiving control apparatus of a data communication system for transmitting data in a communication frame consisting of a packet in which an address, a control code, and a plurality of communication data are packaged. For supplying the plurality of communication data to a central processing unit,
A receiving unit that receives the communication frame, converts and demodulates the received signal into a logical signal, and outputs a received signal; a data link controller that performs processing based on a protocol of a data link layer based on the received signal; and a control unit that controls the data link controller. in the frame reception device and a reception data storage means for storing the plurality of communication data in the received signal, the received data storage means, in each of the plurality of communication data of the first and second of the communication frame Storage means having first and second storage areas for storing certain first and second communication data, respectively, and write address specifying means for specifying write and read addresses of the first and second storage areas, respectively And read address designating means, and whether all of the first and second storage areas are full of stored data. A memory status display unit for supplying a memory status display signal to the data link controller for indicating whether or not the data is not full; and the first and second communication data controlled by the central processing unit and stored in the reception data storage unit. and frame control means for controlling each said first and second storage areas, 1 for storing the respective last address of the first and second communication data as the first and second frame address
It has a byte latch and a multi-byte first-in first-out memory circuit.
If the reception ends during the reception of the communication frame,
In this case, the 1-byte latch has
The frame address at the end of the reception of the last communication frame
Address to the multi-byte first-in first-out memory circuit.
At the end of reception of multiple communication frames before the communication frame
Each frame address is stored, and the received data
Out of the communication frames stored in the storage means.
At the end of communication, the communication frames are
Frame address storage means for clearing the communication frame in units of memory, wherein the data link controller controls the start of reception of the communication frame by displaying the non-full state of the memory status display signal.

[0016]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the frame receiving apparatus of the present invention.

As shown in FIG. 1, a frame receiving apparatus 3 according to the present embodiment includes a receiving unit 11, a data link controller (hereinafter, DLC) 12, and a reception status unit 15 similar to those of the related art, and a FIFO memory. 13, a reception memory 33 that stores reception data, a write address unit 31 that specifies a write address of the reception memory 33, a read address unit 32 that specifies a read address of the reception memory 33,
Memory status section 34 indicating the state of reception memory 33
A frame address buffer 35 for storing the final address of a plurality of received data of each communication frame stored in the reception memory 33; and a frame control unit 36 for managing the received data stored in the reception memory 33 in communication frame units. .

The receiving memory 33 stores the data field DF of the communication frame FF in the same manner as the conventional FIFO memory 13.
Is a dual-port RAM for storing the received data DR of 128 bytes in this embodiment.

The write address section 31 designates an address of the reception memory 33 when the reception data DR is written.
This is a bit counter, and counts up by one every time the received data DR is written in preparation for writing the next received data.
The outputs of the counter are set as write addresses WA7 to WA0 in order from the MSB side. Lower 7 bits, that is, WA6 to
WA0 is input to the reception memory 33 as a real address. The MSB, that is, the WA7, is used as a control bit when the reception memory 33 is used as a ring buffer. The write addresses WA7 to WA0 are supplied to the memory status unit 34 and the frame address buffer 35.

The read address section 32 designates an address of the reception memory 33 when the reception data DR is read.
This is a bit counter, and counts up by one every time the reception data DR is read in preparation for reading the next reception data.
The outputs of the counter are set as read addresses RA7 to RA0 in order from the MSB side. Lower 7 bits, that is, RA6 ~
RA0 is input to the reception memory 33 as a real address. The MSB, that is, RA7, is used as a control bit when the reception memory 33 is used as a ring buffer. The read addresses RA7 to RA0 are supplied to the memory status unit 34 and the frame address buffer 35.

The frame address buffer 35 is a FIFO type buffer that stores the final address of the received data of each communication frame stored in the reception memory 33 as a frame address, and has an 8-bit frame address FA7 to FA0 in order from the MSB side. The data is supplied to the memory status unit 34. The write / read control of the frame address buffer 35 is performed by a frame control unit 36.

The memory status section 34 is supplied with data of the write address section 31, the read address section 32 and the frame address buffer 35, and outputs the state of the reception memory 33. The output of the memory status unit 34 is DL
Status signal RFL supplied to C12 and CPU2
, Which are the status signals FEN to be supplied to the power supply.

The status signal RFL becomes "1" when the reception memory 33 is full. At this time, the write address WA
6-WA0 and read addresses RA6-RA0 match,
In addition, WA7 and RA7 do not match. The status signal FEN becomes “1” at the end of reading of the received data being read by the CPU 2. At this time, the frame addresses FA7 to FA0 match the read addresses RA7 to RA0.

Next, the operation of this embodiment will be described.

Table 1 shows the status when the DLC 12 and the CPU 2 write and read the reception data RD in the reception memory 33, respectively.

[0027]

[Table 1]

First, in state 0 which is an initial state, since the write address section 31, the read address section 32 and the frame address buffer 35 are all 00h, the signal RFL is "0" and the signal FEN is "1". is there. next,
The transmission control device of the transmitting station sends out the first communication frame FFA including the communication data DRA of 60 bytes to the bus.
The DLC 12 of the frame receiving device monitors the communication frame FFA via the receiving unit 11. If it is confirmed in the slave address field FS of the communication frame FFA that the communication frame FFA is addressed to the own station, the control field FC
To check the status signal RFL. As a result of this check, the status signal RFL is '0', that is,
If the reception memory 33 is not full, an acknowledgment signal is returned to the transmission control device, and the data field FD
Of the communication data DRA is started. Communication data DR
Each time one byte of A is received, the status signal RFL is monitored. If the status signal RFL is not "1", the communication data DRA is written to the reception memory 33. When the status signal RFL is “1”, that is, when the reception memory 33 is full, the reception of the communication frame FF is rejected, and the reception operation is terminated without returning an acknowledge signal to the transmission control device. In the present embodiment, 128
Since all the bytes are empty and the status signal RFL is “0”, the DLC 12 writes all of the 60-byte communication data DRA into the reception memory and ends the reception normally. At this time, write address 60h is output from write address section 31 (state 1).

Next, the DLC 12 communicates with the communication frame FFA.
Is set in the reception status section 15, and an interrupt is requested to the CPU 2. In response to the interrupt request, the CPU 2 reads the reception status section 15 and knows the end of the normal reception. Next, the frame controller 36 is controlled to permit reception of the next communication frame FFB. The frame control unit 36 controls the frame address buffer 3
5, the output value 60h of the write address section 31 is written.

Next, the CPU 2 controls the frame control unit 36 to read the address value of the reception memory 33 after the normal reception from the frame address buffer 35. As a result, the frame address buffer 35 stores the address 6
0h is read, and the status signal FEN is changed from "1" to "1".
It changes to 0 '(state 2).

Next, a second communication frame FFB including the communication data DRB of 20 bytes is transmitted from the transmission control device. At this point, the reception control device can normally receive the communication frame FFB because the reception memory 33 is not full, as in the case of receiving the communication frame FFA described above. Therefore, the DLC 12 normally receives the communication frame FFB and writes the 20-byte communication data DRB into the reception memory 33. At this time, the write address section 31 is 80h
Further, since the status signal RFL becomes "1", the reception becomes impossible for the first time (state 3).

In the next state 4, the CPU 2 reads the reception data DRA of the communication frame FFA from the reception memory 33. At this time, the CPU 2 outputs the status signal F
While monitoring until EN becomes '1', receive data R
Read DA.

In the next state 5, the CPU 2 instructs reading of the address at the end of the reception of the communication frame FFB from the frame address buffer 35, the address 80h is read, and the status signal FEN changes to "0" again.

In the last state 6, the CPU 2 reads the reception memory 33 and extracts the reception data DRB until the status signal FEN becomes "1".

In the case of mode 2 in the above-described D2B system, after completion of the reception of 128 bytes of data, in the conventional frame receiving apparatus, the CPU 2 clears the FIFO memory 13 so that the CPU 2 transmits the 128 bytes of data within 2.2 mS. In contrast to the necessity of executing the data reading process, in the present embodiment, reception can be started by reading out data of one byte or more and securing an empty area within the same time. Can be greatly reduced.

Although the embodiment of the present invention has been described above, the present invention is not limited to the above-described embodiment, and various modifications can be made. For example, when the frame address buffer is composed of a one-byte latch and a plurality of bytes of FIFO memory, and the reception is terminated halfway during communication due to a bus failure or the like, the former will terminate the reception of the last communication frame before the termination. By storing the address at the time and the address at the end of reception of a plurality of previous communication frames in the latter, respectively, the reception data stored in the reception memory is sequentially arranged from the reception data at the time of the halfway end among the reception data stored in the reception memory. Clearing of unnecessary received data in communication frame units can of course be applied without departing from the gist of the present invention.

[0037]

As described above, the frame receiving apparatus according to the present invention comprises a frame control section for managing received data stored in the received data storage means in communication frame units, and a plurality of the plurality of storage sections stored in the received data storage means. By providing frame address storage means for storing the final addresses of the plurality of received data of the communication frame as frame addresses, the CPU can distinguish the received data of the plurality of communication frames stored in the received data storage means. If there is an empty area in the data storage means, reception can be started, so that the processing load on the CPU can be greatly reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a frame receiving apparatus according to the present invention.

FIG. 2 is a block diagram illustrating an example of a conventional frame receiving apparatus.

FIG. 3 is a diagram illustrating a configuration of a communication frame of the D2B system.

[Explanation of symbols]

 1, 3 frame receiving device 2 CPU 11 receiving unit 12 DLC 13 FIFO memory 14, 34 memory status unit 15 reception status unit 31 write address unit 32 read address unit 33 reception memory 35 frame address buffer 36 frame control unit

Claims (2)

(57) [Claims] 1. A plurality of communication data are supplied to a central processing unit constituting a reception control device of a data communication system for transmitting data by a communication frame composed of a packet in which an address, a control code, and a plurality of communication data are packaged. A receiving unit for receiving the communication frame, converting and demodulating the communication frame into a logical signal, and outputting a received signal, a data link controller performing a process based on a protocol of a data link layer, and the data link controller in the frame reception device and a reception data storage means for storing the plurality of communication data in the received signal under the control of, the received data storage means, each of said plurality of first and second of the communication frame First and second storing first and second communication data, which are communication data, respectively. Storage means having a storage area, and write address designation means and read address designation means for designating write and read addresses of the first and second storage areas, respectively. A memory status display means for supplying a memory status display signal to the data link controller for indicating whether or not the data is fully filled with stored data to the data link controller; and wherein the memory status display means is controlled by the central processing unit and stored in the received data storage means. Frame control means for managing the first and second communication data for each of the first and second storage areas; and the first and second frame addresses for the final addresses of the first and second communication data, respectively. 1-byte latch and multiple-byte first-in first-out memory circuit
And the reception is terminated during the reception of the communication frame.
In this case, the 1-byte latch contains the data after the end of reception.
The frame at the end of the reception of the previous last communication frame
The address is stored in the multi-byte first-in first-out memory circuit.
End of reception of multiple communication frames before final communication frame
The frame address at the time of
Out of the communication frames stored in the data storage means.
At the end of reception, the communication frames are
A frame address storage unit that clears the frame in frame units , wherein the data link controller controls the start of reception of the communication frame by displaying the memory status display signal indicating the non-full state. Wherein said write addressing means and the read addressing means, and wherein the obtaining Bei a predetermined number of bits of the counter which increases by one each count value for each writing and reading of the communication data The frame receiving apparatus according to claim 1.