JPS59230346A - Buffering system of transmission/reception data of transmitter - Google Patents

Abstract

PURPOSE:To attain efficiently buffering by assigning dynamically plural transmission/reception buffer memories to plural terminal devices in a transmitter where plural terminal devices including a host computer are provided to each station coupled to a bus transmission line. CONSTITUTION:A terminal device 8 and the host CPU (computer) 9 perform transmission/reception of data to other transmitters by utilizing a transmission line by means of a transmission controller 4. A signal of the terminal device 8 and the host CPU9 is given to the transmission controller 4 via a data bus generation multiplexer 13, reception buffers 111-, transmission buffers 121- and a local bus 5. The transmission and reception buffers 111-, 121- are utilized not fixedly but dynamically under the control of a local computer 10.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a buffering method for transmitted and received data in a transmission device in which a plurality of terminal devices including computers are connected to one station.

This type of transmission device has the station configuration shown in FIG. A transmission line 1 connecting a plurality of stages g7 is connected to a transmitter 2 and a receiver 3KxF) for each station.
Ru. Information sent and received by the transmitter 2 and the receiver 3 is transferred to the station local bus 5 via the transmission controller 4, and this information is sent to each terminal device or host computer via a transmission buffer 6 in a dedicated interface 6.7. ,.

7, or receive buffer 6! - Temporarily placed at 7t,
It is exchanged with the terminal device 8 and the host computer 9 via the Inter7Ace 6.7. The distribution of information between the local computer 10 td transmission controller 4 and each inter 7 ace 6.7 is used for control. The data flow between each interface 6.7 and the transmission controller 4 is performed by DMA transfer, with the broken line arrows in the figure showing the transmission path and the solid line arrows showing the reception path.

A station with such a configuration has the following problems.

(1) Each terminal device and computer is provided with a dedicated transmitting/receiving buffer 6□H6t, 7t t 7t.

When processing on the host computer/computer side is slow, the receiving port 7 tends to become busy.

(2) When the number of stations is large, the amount of information destined for a certain terminal device or host computer increases and the reception buffer tends to become busy.

(3) Even if the data transmission speed of transmission path 1 is high (1)
Similar to the above, it is easy to cause the receive buffer to be busy.

(4) During transmission, as the number of terminal devices and computers connected to one station increases, it takes longer to flush out data from the transmission buffer.

Blank transmission buffer empty 1! The terminal device side is forced to wait for the next transmission data transfer until the end.

In order to solve all such problems, each terminal device.

A double buffer may be provided on the combinator side, but this increases the buffer memory capacity and makes it difficult to use it efficiently. For example, depending on the operational status of the system, data may be exchanged frequently with one terminal device while data is exchanged only every nine days with another terminal device.

Further, the double-balance method described above has the following disadvantages from the perspective of the transmission controller 4.

(5) The transmission controller requires processing means for receiving and transmitting the next data by selecting one of the plurality of buffers.

(6) The transmission controller requires means for determining whether each receive buffer is busy or not because of item (5).

(7) When there are simultaneous transmission requests from a plurality of terminal devices, the transmission controller requires priority processing of the transmission buffer in addition to priority processing of the terminal devices.

(8) As data transmission speeds increase, it becomes difficult to provide highly intelligent functions to transmission controllers.
It becomes difficult to process items (5), (6), and (7) above.

The present invention is a buffering method that dynamically allocates a plurality of transmitting and receiving buffer memories to a plurality of terminal devices, and efficiently processes data regardless of increasing the number of terminal devices or combiners or increasing the data transmission speed of the transmission line. The purpose is to obtain a buffering method that is possible.

FIG. 2 is a station configuration diagram showing one embodiment of the present invention. The four-car bus 5 includes reception backup memories 111, 1t, . . . and transmission buffer memories 12!, which are collectively held in the station. I... are combined.

Terminal equipment 8. The device 6.7 is connected to the computer 9, communicates with the local computer 10 at the time of reception, and stores the reception buffer memory 111゜11.
A reception channel 6h71 for receiving data on the receiving side and a transmission channel 64.74 for communicating with the local computer 1o at the time of transmission and transmitting data to the transmission backup memories 121 and 121 side are provided. Transmit/receive back memory lb t llm-island, 12. and Inter 7 Aces 6.
7 transmitting and receiving channels 6m, 64, 7g, 7
A data bus generation multiplexer 13 is provided between
'L, this multiplexer 13' is also coupled to the local *y fuse 10 via the local bus 5, and dynamically allocates buffer memory for transmitted and received data based on commands from the computer 1°.However, each terminal device Alternatively, the number of sending/receiving buffer memories allocated to the host combiner can be restricted to prevent one terminal device or host computer from occupying the entire sending/receiving buffer memory, and even if the station as a whole has a large amount of sending/receiving data, each terminal device Or a combination tool - eliminates the extreme imbalance of evening time.

In such a configuration, data transmission from the terminal device 8 or the host combiner 9 to the transmission line 1 side is carried out through the transmission channel TX of the interface as indicated by the broken line arrow in the figure.
from the transmit buffer memory 1 through the multiplexer 13.
21 and is transmitted through the n1 transmission controller 4. Further, data reception from the transmission path 1 side is carried out from the transmission controller 4 to the reception buffer memory 11. Once stored in n1 multiplexer 13
The data is received by the terminal R8 or the host computer 9 through the Inter7Aids reception channel RXi.

The data bus between the transmission controller 4 and the buffer memory, and the data bus between the buffer memory and each terminal device and small computer are all controlled by the local computer 10. Finally, the local computer 10 notifies the transmission controller 4 of the transmitting buffer and receiving buffer to be used next time in advance by specifying addresses. In this case, there is no need for the transmission controller to be concerned with the four transmitting/receiving buffers, and it can be used simply by determining whether or not it is busy. On the other hand, the terminal device 8. For the host computer 9, in the case of transmission, the local combiner 10 generates a data bus to the transmission buffer for the terminal device that generated the request and the host computer, and in the case of reception, it sends a data bus to the transmission buffer. A data bus is generated between the terminal device and the receive buffer in which data addressed to the host computer is stored. By doing so, each terminal device and the host computer can share a plurality of buffers, thereby absorbing the lack of processing capacity on the terminal device side. Further, the transmission controller 4 essentially controls a single transmitting buffer and a single receiving buffer, and only needs to monitor the busy state of the single buffer, thereby reducing the burden.

The transmission and reception processing procedure will be explained in detail below. 1. Regarding data transmission and transmission, the maximum number of bytes is determined as the maximum transmission amount (1 packet).ns transmission/reception buffer 111
, 11. ,..., 12+-12t... has a capacity of the maximum number of bytes (several kilobytes).

First, the communication between the local computer and the host computer or terminal device at the time of transmission is the following procedures (A) to (Q).

(A) . . . An interrupt is sent from the host computer 9 to the local combiner 10 indicating that transmission is possible. This occurs for the terminal device 8 (TX RDY). At this time, the local computer 10 creates a data bus between the empty transmission buffer, the host computer, and the terminal device.

(B)...When the host computer or terminal device generates data to be transmitted, it writes the data into the transmission buffer specified in paragraph (4).The number of bytes of this data is up to the maximum number of bytes that the buffer has. arbitrarily within the range of n.

(C)...Host: When the monitor or terminal device writes all the transmission data to the transmission buffer, it generates an interrupt to the local computer to start transmission (
TX Go).

(Event...The local computer can recognize which host computer or terminal device was given the transmission buffer in the interrupt in (0), so by reading the TXGO interrupt code, it can identify which host computer or terminal device it has given the transmit buffer to.) It is immediately recognized whether the transmission data is stored in the transmission buffer given to the TXGO.In addition, by giving priority to TXGO interrupts and assigning interrupt codes to each device, even if there are interrupts at the same time, the local computer can I never recognize it.

(g))…4-Cal Combi A-Tach transmission control 4-Ra 4
A data bus is generated between the transmission controller and the transmission buffer in which the transmission request information and busy transmission data are stored.

(Pi...The transmission controller that has been given the transmission request will make sure that all the data stored in the transmission buffer is blank (Emp).
The data is read and transmitted until t7). Then, when the transmission of all the data is completed, the 4-kalpunbiter is notified by an interrupt.

(G)...4-Cal computer recognizes that the transmission buffer is empty by the transmission end interrupt from the transmission controller, and sends the next host computer or terminal device (A) or ( Returning to the process regarding item C').

Transmission is performed according to the above procedure, but when the amount of data to be transmitted is stored in the transmission buffer, the terminal device 8 or host computer 9 interrupts (TX Go).
to notify the local computer 10. Therefore, the local computer 10 is not concerned at all with the completion of data storage in the transmission buffer, and the application software of the host computer or terminal device recognizes this.

On the other hand, since the host computer or terminal device instructs the local computer 10 in advance about the number of bytes of data to be sent, the local computer 10 recognizes the empty state from the number of bytes. . The recognition Kid, 4-Cal combiner 10 sets the address and count value (number of bytes of data to be transmitted) of the transmission buffer in the DMA controller, and sends a transmission request to the transmission controller 4 at the same time. Issue a start command. Then, the count-up signal from the DMA controller causes the transmission controller 4 to complete the transmission, and generates an interrupt sound for the local computer to indicate the end of transmission, and the local computer 10 blanks out the transmission buffer that was being given to the transmission controller at that time. Recognize what has happened.

In this way, data is stored in the transmission buffer and its output is completed, but a transmission start request (TXGO) to the quadrilateral computer regarding one transmission buffer memory
), it takes a relatively long time until the local computer can transmit data (TXRDY) after data transmission. For this reason, in the conventional configuration, even if the host, the computer, or the terminal device attempts to transmit all data for several packets in succession, the transmission backup capacity is insufficient. In contrast, in the present invention, it is possible to dynamically allocate a plurality of transmitter panzer memories to each terminal device, so that the local combiner can immediately send other messages to the host computer or terminal device from a transmission start request. Transmission capability for the transmission backup memory will be given.

Next, the processing procedure at the time of reception will be explained.

Normally, the format for data transmission through a transmission line is as shown in Figure 3, with 7 lags F indicating the start and end of the information, addresses A of the station and terminal equipment, and control 4-L C. , a data word length (or byte length) WL, data I of up to several kilobytes, and an error check code FCS.

For data received in such a format,
The host computer, terminal device, and four-cal computer system are based on the following (2~(R)).

(6)...Host computer9. Can be received from the terminal device 8 to the local computer 10 by interrupt (R
X ENB). By providing a priority code and an interrupt hood for this interrupt, the local computer knows which devices can receive it.

(L)...The local combiner generates a data bus between the transmission controller 4 and one reception buffer memory.

---The transmission controller generates data at address A corresponding to the host controller or terminal device of its own station from the information taken in in the format shown in Figure 3 using the data bus formula n. A of the received pan indication formats
, C, WLf to the local computer and transfer the amount of data to the receiving hacka memory.

(Incorporated)...When the transmission controller has finished transferring all data to the reception backup memory, it notifies the local combination unit of the completion of reception by an interrupt.

(0)...The local computer generates a data bus for the next reception buffer memory to the transmission controller at the reception end interrupt.

(P)...The local computer reads the address Ai of the received data, and if the host computer or terminal device corresponding to the address is receivable (RX ENB), the data is stored between the receive buffer memory and the receivable device. Generate data bus.

(Q)...The local computer generates an interrupt for the terminal device or host computer that generated the data bus, and the received data for the device is stored in the specified receive buffer memory. Let me know that you are there (RX
DONK).

(RJ... After receiving the interrupt, the host computer or terminal device reads the data from the reception buffer memory, and then notifies the local computer that it is ready to receive the next data (RXENB) by interrupting it.

In such reception processing, the four-cal computer recognizes that the amount of data specified by the word length (byte length) WL has been stored in the reception buffer memory by the reception end interrupt from the transmission controller. 6 again. The empty state of the reception buffer memory is recognized by the local computer by a reception ready (RX ENB ) interrupt from the data reception host computer or terminal/device. This recognition is performed by setting the number of words WE in the transmission format in the DMA by the local computer, and counting up as the data is read by the data receiving host computer or terminal device.

In the case of such transmission/reception data, the data bus generation multiplexer 13 can be configured as shown in FIG. 4 to realize its function. This figure shows a case in which two terminal devices share two transmitting buffer memories, seven receiving buffers, or one transmitting buffer memory and receiving backup memory. Backa memory 14. , 14. are respectively bidirectional bus drivers 15s t 15! K-coupled,
Two terminal devices (or host combiners) 161, 161 each including an interface are connected to a multiplexer 17. , 17. bus driver 151 is coupled to multiplexer 17.n. and 17. Connects both n1 and bus driver 15. is multiplexer 17. and 17.
It is combined with both. Bus driver 15, , 15. switches the data input/output direction in response to the n direction designating signal DIR supplied from the four-cal computer 10, and performs data input/output operations in accordance with the data input/output enable signal ENB supplied from the local computer 10. The multiplexers 17s, 17t are connected to bidirectional bus drivers 151 or 15. t-Select.

As described above, the present invention does not have a transmission/reception backup memory fixedly provided in each terminal device or host computer, but allows a plurality of devices to share a part of the memory and use it in a terminal device with a slow processing speed. This greatly reduces the chance that the receiving buffer of the receiver becomes busy, and allows for more efficient use of buffer memory than when a double buffer is used. Also,
Instead of having a small intelligent transmission controller manage the sending and receiving buffer memory, it is managed by a highly intelligent local computer, which reduces the burden on the transmission controller, reduces the amount of hardware, and makes it smaller and faster. Even in transmission, power consumption can be reduced. In addition, the highly intelligent local computer manages the sending and receiving buffer memory and determines priorities during sending, and can respond flexibly to changes in the number of terminal devices connected to the station.

[Brief explanation of the drawing]

Fig. 1 is a station configuration diagram for fully explaining the conventional batsuring system, Fig. 2 is a station configuration diagram showing an embodiment of the present invention, Fig. 3 is a format configuration diagram of transmitted and received data, and Fig. 4 is a station configuration diagram showing an embodiment of the present invention. FIG. 3 is a four-dimensional diagram illustrating one embodiment of the data bus generation multiplexer in FIG. 1... Transmission path, 2... Transmitter, 3... Receiver, 4
. . . transmission controller 4, 5 . . 4 karbus, 6.
7...Interface, 8...Terminal device, 9...
・Host combiner, 10...Local computer, Ilt, 11tlit...Reception buffer memory, 121.12. ...Transmission buffer memory, 13.
...Data bus generation multiplexer, 14. . 14, . . . buffer memory, 15. , 15. ...
Bidirectional bus driver, 161, 16t... terminal device, 17s - 17t... multiplexer. 1 package Showa 59-230346 (8)

Claims (2)

[Claims] (1) In a transmission device in which a plurality of terminal devices including a host computer are provided at each station connected via a transmission path, the system is extended to the stations and controls data reception on the transmission path and data transmission on the transmission path. The transmission controller 4-2 is connected to the transmission controller 4-2 by a p-cal path, and a plurality of transmission backup memories for temporarily storing transmission data are connected to the transmission controller 2 by a cal-path. n
a plurality of reception buffers 7 memories that temporarily store received data; and data from a specified number of reception buffer memories among said reception backup memories is provided to a specified number of terminal devices; A data bus generating multiplexer for supplying transmission data from a designated terminal device of the terminal devices to the transmission buffer memory, a data bus generation multiplexer coupled to the four-car bus, and a link between the transmission controller and the transmission and reception buffer memory. and a 54-cal computer which generates a data bus between the backup system and the terminal device under the control of the multiplexer, and includes a 54-cal computer capable of transmitting and receiving data to and from each of the terminal devices. The local combiner allocates a plurality of reception buffer memories and selects an empty buffer memory among the allocated buffer memories. 1. A buffering method for transmitting and receiving data of a transmission device, characterized in that transmitting or receiving data is stored and output is controlled by using the transmitter. (2) The above-mentioned local controller is the above-mentioned transmission controller.
Transmission and reception data of the transmission device according to claim 1, characterized in that the address of the buffer memory is notified to the transmission controller 4-2 on the data bus between the controller and the transmission or reception buffer memory. buffering method.