JPH1070362A - 基板を結合する方法および構造 - Google Patents
基板を結合する方法および構造Info
- Publication number
- JPH1070362A JPH1070362A JP9143276A JP14327697A JPH1070362A JP H1070362 A JPH1070362 A JP H1070362A JP 9143276 A JP9143276 A JP 9143276A JP 14327697 A JP14327697 A JP 14327697A JP H1070362 A JPH1070362 A JP H1070362A
- Authority
- JP
- Japan
- Prior art keywords
- conductive
- substrate
- adhesive
- holes
- conductive adhesive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
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- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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Abstract
よび構造の結合方法を提供する。 【解決手段】 本方法は、半導体素子(26)を基板
(18)に結合する接着挟持構造(11)の使用を含
む。接着挟持構造(11)は、非導電性接着貼合材(1
2)および導電性接着バンプ(13)を有する。導電性
接着バンプ(13)は、半導体素子(26)上の導電性
バンプ(27)と、基板(18)上に位置する導電性金
属パッド(21)との間の導電路を与える。別の実施例
では、導電性接着剤(34)を、プリント回路基板(3
8)上に位置したスクリーンまたはステンシルで印刷し
て、バイア内に導電性接着バンプ(33)を形成する。
次いで、導電性接着バンプ(33)に隣接したプリント
回路基板(38)の上へ、非導電性接着(52)をスク
リーンまたはステンシルで印刷する。この後、この構造
に半導体ダイを接続する。
Description
素子アセンブリに関し、更に特定すれば基板を接続する
方法および構造に関するものである。
ドなどの用途において、急速にえり抜きの組立技法にな
りつつある。フリップ・チップ技術を用いて、半導体チ
ップを薄いプリント回路基板に接続し、基板アセンブリ
を形成する。次いで、この基板アセンブリを、例えば、
クレジット・カード素子内に組み込んで、スマートカー
ドを提供する。一旦クレジット・カード素子内に組み込
まれた半導体チップは、口座集計機能(account trackin
g feature)およびセキュリティ機能をカード保持者に提
供する。
プ組立工程においては、バンプを形成した半導体チップ
を、プリント配線基板即ちプリント回路基板に結合す
る。プリント回路基板は典型的に樹脂材料から成り、両
面にはパターニングされた金属層を有する。このパター
ニングされた金属層は、コンタクト・パッドおよび導電
路を形成する。金属層の接続には典型的にメタライズさ
れた孔(metallized via)を用いる。
バンプを、プリント回路基板上の対応する金属接点パッ
ドに接続する。次いでこのアセンブリを加熱し、導電性
接着剤を硬化させる。次に、半導体ダイとプリント回路
基板との間のギャップおよび隣接するバンプ相互間のギ
ャップに、非導電性封入材または貼合材(laminant)を配
置する。これは一般に、「アンダフィル」工程と呼ばれ
ている。次いでこのアセンブリを再加熱し、非導電性封
入材を硬化させる。
かの欠点がある。第1に、両面に金属層を有するプリン
ト回路基板は高価である。また、導電性接着剤を半導体
バンプに接触して配置するのに用いる工程にはばらつき
があり得るため、塗布する接着剤の量が一貫しないこと
がある。このため、開放および/または短絡により素子
が動作不能となることがある。更に、導電性接着剤硬化
工程は、半導体ダイに応力を加えることになる。これは
取りわけ、半導体ダイおよびプリント回路基板間の熱膨
張率の差によるものである。かかる応力は半導体ダイに
損傷を与える可能性がある。加えて、アンダフィル工程
は一貫性に欠けるため、特に導電性接着剤/非導電性接
着剤界面で空隙を残す可能性がある。かかる空隙は信頼
性の問題を起こし得るものである。更に、従来のスマー
トカードのフリップ・チップ工程は、多数の工程から成
るため高価である。
が、信頼性が高く、コスト有効性に優れ、また効率的な
基板接続方法および構造が要望されている。
構造の結合方法は、接着挟持構造を用いて半導体チップ
をプリント回路基板に接続する。接着挟持構造は、非導
電性接着剤およびこれに結合された導電性接着バンプを
有する。このバンプを半導体基板の孔内に堆積する。孔
は一方側に導電性金属パッドを有し、バンプと共に導電
路を与える。こうして得られる中間アセンブリは、次レ
ベルの組立への対応が容易である。また別の実施例にお
いては、スクリーン・マスクを用いて導電性接着剤およ
び非導電性接着剤を選択的に堆積する。
基板モジュールを形成する方法および構造に関するもの
である。更に特定すれば、本発明は、接着挟持構造(adh
esive interposer structure) を利用して半導体チップ
を薄いプリント回路基板に接続する。挟持構造は、接着
予備成形構造から成る。あるいは、接着挟持構造は、例
えば、マスキング技法を用いて、薄いプリント回路基板
上に直接に形成する。挟持構造によって、特にスマート
カードの用途における組立工程が大幅に簡略化される。
段階における、接着挟持構造、即ち、接着バンプ予備成
形構造11およびプリント回路基板,基板即ちベース基
板18の拡大断面図を示す。接着挟持構造11は、非導
電性接着剤即ち封入材部分12,およびかかる非導電性
接着部分12に結合した複数の導電性接着バンプ,導電
性接着部分即ち導電性接着ドット13を含む。接着挟持
構造11は、接着バンプ予備成形物(adhesive bump pre
form) または「エリア・ボンディング導電性(AB
C)」フィルム接着剤とも呼ばれている。
エポキシ接着剤から成る。好適実施例において、非導電
性接着部分12は、部分的に硬化した(即ちB−ステー
ジ)酸化物、またはシリカ充填誘電体エポキシ樹脂(例
えばノボラック・タイプ(novolac-type))から成る。導
電性接着バンプ13は、非導電性接着部分12と同じ樹
脂から成り、銀などの導電性充填剤を加えて、導電性の
エポキシ樹脂とすることが好ましい。典型的に、導電性
充填剤は、導電性接着剤を形成する全成分の重量の約6
5〜85%である。接着バンプ予備成形材料は、マサチ
ューセッツ州 Needham Heightsの Merix Corporationか
ら入手可能である。
ンプ13の配置即ち位置決めは、用途の関数である。即
ち、この配置は、製造業者の電子素子設計およびプリン
ト回路基板設計の要求によって異なる。オプションとし
て、接着挟持構造11は更に、支持を強化するために、
キャリア膜裏当て(carrier film backing)即ち支持膜1
4を含む。裏当て14は、例えば、ポリエチレン・テレ
フタレート樹脂フィルム(一般にMYLAR(登録商
標)として知られている)などから成る。
0ないし約200ミクロンの範囲の距離16の長さだ
け、非導電性接着部分12より上に延在する(即ち露出
された高さを有する)。距離16は、導電性接着バンプ
13が導電性金属パッド21(以下で説明する)に接触
するよう、孔19(以下で説明する)の深さによって調
整する。導電性接着バンプ13は、典型的に、直径約2
00ないし650ミクロンであり、これも用途の関数で
ある。
は、かかる基板18の一方側から対向側まで達する。孔
19は、基板18の一方側ににある導電性金属パッド2
1にて終端する。導電性金属パッド21は、典型的に、
銅/ニッケル/金から成る。導電性金属パッド21の一
部は、部分的に孔内部にまで入っていると好ましい。孔
19と導電性金属パッド21との組み合わせは、本発明
の重要な特徴である。第1に、導電性金属パッド21が
基板18の一方側にしかないので、両主面に金属層を有
し、また完全にメタライズされた孔を有する従来技術の
基板に比較すると、コストの低減が図られる。また、こ
れによって製造業者は、孔19内に導電性接着バンプを
配置して、最終基板モジュールの厚さを最少限に抑える
ことができる。これは、厚さが重要なパラメータである
スマートカードの用途において特に重要である。
板から成る。適切な材料としては、FR4,エポキシ・
ガラス,ポリエステル,ポリイミド等がある。基板18
の厚さは、用途によって異なる。スマートカードの用途
においては、基板18は約50〜250ミクロンの厚さ
であることが好ましい。
露出される高さによって異なり、また導電性接着バンプ
13の各々が導電性金属パッド21に接触するよう固定
する。孔19の各々の直径は、導電性接着バンプ13の
直径よりも大きく、また導電性接着剤の流動性によって
異なる。例えば、上述の導電性接着剤では、孔19の直
径は導電性接着バンプ13の直径よりも約20ミクロン
大きい。先に示したように、導電性接着バンプ13の配
置は、孔19の位置に対応するよう設計される。基板1
8のような基板は、フランスのMante-la-JolieのMicro-
Connectique Technologies(MCTS)から入手可能であ
る。
の基板構造の拡大断面図を示す。導電性接着バンプ13
が、孔19の内対応する1つに組み合わされ、その中に
あって、または結合されて、中間アセンブリ構造24が
得られるように、接着挟持構造11を基板18に結合す
る。図2に示すように、導電性接着バンプ13の各々が
導電性金属パッド21に結合することにより導電路が得
られる。
ク・タイプ樹脂から成る場合、まず約2ないし4 psi
(1平方インチ当たりポンド)の圧力を加え、またこの
構造を約80ないし約100℃で約1ないし2秒間加熱
することにより樹脂に存在する溶剤を完全に乾燥させる
ことにより、接着挟持構造11を基板18に結合する。
また、熱によって樹脂を部分的に硬化(即ちB−ステー
ジとする)させてもよい。この時点で中間アセンブリ構
造24を、保管のために簡便な方法として、キャリア
(例えばリール・キャリア,ワッフル・パックなど)の
中に入れることができる。例えば、基板18の製造業者
が、接着挟持構造11を基板18に結合し、部分的に挟
持構造を硬化させ、こうして得られた中間アセンブリを
パッケージ化して半導体チップ供給業者または製造業者
に出荷することができるので、これは従来技術に比べる
と大きな利点である。これによって、半導体チップ供給
業者に求められる処理がかなり簡略化される。
立機器(例えばテープおよびリール機器)を利用して、
半導体チップを中間アセンブリに接続することができ
る。こうして、チップ供給業者は、半導体チップへの応
力により信頼性の問題を生じ得る、従来技術の多工程に
わたる接着剤塗布工程および硬化工程を用いる必要性を
回避する。本発明による方法ではアンダフィル・プロセ
ス(underfill process)も不要なので、導電性接着バン
プ/非導電性封入材界面における空隙の問題も低減され
る。また、接着挟持構造11を用いることにより、導電
性接着バンプの寸法のばらつきが減るため、開放および
/または短絡故障の発生数が減少する。
26を接着挟持構造11に結合する前に、図3に示すよ
うに、支持膜14を除去する。好ましくは、支持膜14
の除去は、上述のように基板アセンブリをキャリア装置
に配置する前に行う。半導体素子26は、導電性金属パ
ッド21に電気的に結合する複数の導電性バンプ,部分
または隆起部分27を有する。
トローラ素子やメモリ素子などの集積回路素子から成
る。導電性バンプ27は、典型的に、銅,金またはニッ
ケル金等のはんだ付け可能な堆積金属(deposited solde
rable metal)から成り、既知の処理法(例えばワイヤ・
バンピング,電気めっき,蒸着など)を用いて形成され
る。別の実施例(図示せず)においては、導電性部分2
7は金属パッドまたは金属部分から成り、バンプを使用
しない。
するため、半導体素子26を接着挟持構造11に位置合
わせし、これと接触するように圧入することにより、導
電性バンプまたは部分27の各々が、対応する導電性接
着バンプ13および対応する導電性金属パッド21に結
合し、図4に示す基板構造,フリップ・チップ・アセン
ブリ,基板モジュール即ちスマートカード・モジュール
28を設ける。次いで基板モジュール28を所定の高温
に晒すことによって、硬化させる。温度は適用する接着
剤の関数である。例えば、接着挟持構造11がノボラッ
ク・タイプ樹脂から成る場合、基板モジュール28を約
45分間、約155ないし165℃に晒す。
ド本体,素子または基板29などの次レベルのアセンブ
リに結合されるまで、基板モジュール28を保管する。
図5は、基板モジュール28の埋め込まれたスマートカ
ード素子即ちアセンブリを示す簡略断面図である。基板
モジュール28は、次レベルの組立における自動化に対
応するため、テープおよびリール・キャリアまたはワッ
フル・パック・キャリア内に保管すると好都合である。
を形成する別の方法の拡大断面図を示す。図6は、複数
の孔39および複数の金属コンタクト・パッド41を有
する基板38を示す。孔39の各々に導電性接着バンプ
33を選択的に堆積即ち配置するため、開口43を有す
るスクリーン・マスクまたはステンシル42を用いる。
開口43の配置は孔39の位置に対応する。ブレード装
置36を用いて、スクリーン・マスク42上に(矢印3
7に示すように)バルク状導電性接着剤34を塗布し
て、孔39の各々に導電性接着剤34を選択的に堆積
し、図7に示す構造を得る。好適実施例においては、導
電性接着剤34は、Meric Corporation から入手可能な
1873−14などのB−ステージ可能エポキシ(B-sta
geable epoxy) から成る。
着バンプ33を部分的に硬化させる。導電性接着バンプ
33が1873−14から成る場合、この構造を約30
秒間、約80ないし100℃に晒す。部分的硬化工程の
後、図8に示すように、開口47を有する第2スクリー
ン・マスクまたはステンシル46を用いて、導電性接着
バンプ33に隣接して、非導電性接着剤即ち封入材52
(即ちアンダチップ(underchip) 封入材)を選択的に堆
積即ち配置する。第2スクリーン・マスク46は、スク
リーン・マスク42とは逆のパターン(即ち密度)を有
する。ブレード装置56を用いて、第2スクリーン・マ
スク46上(矢印57に示すように)、また基板38の
表面にバルク状非導電性接着剤53を塗布し、図9に示
す中間アセンブリを得る。
電性接着部分12と同じ材料から成る。中間アセンブリ
61は、図2および図3に示す中間アセンブリ24と同
様、簡単に半導体チップに取り付けることができる。半
導体チップを取り付けた後、得られた構造を高温に晒し
て非導電性接着剤52を硬化させ、また導電性接着バン
プ33を更に硬化させれば、次レベルの組み立て準備が
整った基板モジュールが得られる。別の実施例において
は、最初に非導電性接着剤52を堆積し、次いで導電性
接着バンプ33を形成する。
いて説明したことが認められよう。例えば、プリント回
路基板と半導体ダイとの間に接着挟持構造を用いること
により、組立工程の大幅な簡略化、および信頼性向上が
図られる。これは、製造コストおよび投資の節約とな
る。
したが、これは例示の目的のために過ぎず、特許請求す
る本発明の範囲を限定するものとして解釈すべきもので
はない。例えば、接着挟持構造を最初に半導体素子に結
合し、その後にプリント回路基板に結合してもよい。ま
た、図9に示す構造を設ける際、選択分配法などの他の
技法も適している。
断面図。
断面図。
断面図。
断面図。
拡大断面図。
板構造の拡大断面図。
板構造の拡大断面図。
板構造の拡大断面図。
板構造の拡大断面図。
Claims (5)
- 【請求項1】基板モジュールを形成するための基板の結
合方法であって:ベース基板(18)および接着挟持構
造(11)から成る第1基板アセンブリ(24)を設け
る段階であって、前記ベース基板(18)は複数の孔
(19)を有し、前記接着挟持構造(11)は、非導電
性封入材(12)および該非導電性封入材(12)に結
合した複数の導電性バンプ(13)を有し、前記複数の
導電性バンプ(13)の内少なくとも1つが前記複数の
孔(19)の内の1つに結合するように、前記接着挟持
構造(11)を前記ベース基板(18)に結合する段
階;および一方の表面上に形成された複数の導電性バン
プ(27)を有する第2基板(26)を前記第1基板ア
センブリ(24)に結合する段階であって、前記複数の
導電性バンプ(27)の内少なくとも1つを前記複数の
孔(19)の内1つに結合して基板モジュール(28)
を形成し、前記接着挟持構造(11)を前記第2基板
(26)と前記ベース基板(18)との間に配する段
階;から成ることを特徴とする方法。 - 【請求項2】前記基板モジュール(28)をカード本体
(29)に結合してスマートカード・アセンブリを形成
する段階を更に含むことを特徴とする請求項1記載の方
法。 - 【請求項3】1対の基板を接続する方法であって:第1
基板(38)を設ける段階であって、該第1基板(3
8)の一方側から反対側まで達するする複数の導電性孔
(39)を有する第1基板(38)を設ける段階;前記
複数の導電性孔(39)内に導電性接着剤(34)を選
択的に堆積し、複数の導電性接着部(33)を設ける段
階;前記複数の導電性孔(39)に隣接した前記第1基
板上に非導電性封入材(53)を選択的に堆積して、ア
ンダチップ封入材(52)を設ける段階;一方の表面上
に形成された複数の導電性隆起バンプ部(27)を有す
る第2基板(26)を設ける段階;および前記複数の導
電性隆起部(27)を前記複数の導電性接着部分(3
3)に結合する段階;から成ることを特徴とする方法。 - 【請求項4】フリップ・チップ基板モジュール構造であ
って:主面上に形成された複数の導電性部(27)を有
する半導体素子(26);基板(18,38)であっ
て、該基板の一方側(18,38)から反対側まで達す
る複数の孔(19,39)を有する基板(18,3
8);および非導電性封入材部(12,52)および該
非導電性封入材部(12,52)に結合された複数の導
電性接着部分(13,33)を有する挟持予備成形構造
(11,33,52);から成り、 該挟持予備成形構造(11,33,52)は、前記複数
の導電性接着部分(13,33)の内少なくとも1つが
前記複数の孔(19,39)の内の1つに入るように前
記基板(18,38)に結合し、前記半導体素子(2
6)は、前記複数の導電性部分(27)の内少なくとも
1つが前記複数の孔(19,39)の内の1つに結合す
るように前記挟持予備成形構造(11,33,52)に
結合されることを特徴とするフリップ・チップ基板モジ
ュール構造。 - 【請求項5】請求項4記載の構造であって:前記フリッ
プ・チップ基板モジュールはスマートカード・モジュー
ル(28)を含み、前記構造はカード本体(29)を更
に有し、前記スマートカード・モジュール(28)は前
記カード本体(29)に結合されてスマートカードを形
成することを特徴とする請求項4記載の構造。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/654,466 US6022761A (en) | 1996-05-28 | 1996-05-28 | Method for coupling substrates and structure |
US654466 | 1996-05-28 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH1070362A true JPH1070362A (ja) | 1998-03-10 |
JP3962449B2 JP3962449B2 (ja) | 2007-08-22 |
Family
ID=24624967
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP14327697A Expired - Fee Related JP3962449B2 (ja) | 1996-05-28 | 1997-05-15 | 基板を結合する方法および構造 |
Country Status (4)
Country | Link |
---|---|
US (1) | US6022761A (ja) |
EP (1) | EP0810649B1 (ja) |
JP (1) | JP3962449B2 (ja) |
DE (1) | DE69725926T2 (ja) |
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-
1996
- 1996-05-28 US US08/654,466 patent/US6022761A/en not_active Expired - Lifetime
-
1997
- 1997-05-12 EP EP97107710A patent/EP0810649B1/en not_active Expired - Lifetime
- 1997-05-12 DE DE69725926T patent/DE69725926T2/de not_active Expired - Fee Related
- 1997-05-15 JP JP14327697A patent/JP3962449B2/ja not_active Expired - Fee Related
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JP2012199312A (ja) * | 2011-03-18 | 2012-10-18 | Fujitsu Ltd | 基板ユニット、及び、基板ユニットの製造方法 |
Also Published As
Publication number | Publication date |
---|---|
US6022761A (en) | 2000-02-08 |
DE69725926D1 (de) | 2003-12-11 |
JP3962449B2 (ja) | 2007-08-22 |
EP0810649A3 (en) | 1998-12-23 |
EP0810649B1 (en) | 2003-11-05 |
DE69725926T2 (de) | 2004-05-06 |
EP0810649A2 (en) | 1997-12-03 |
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