JPH103424A - Fifo memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent te body cut of a picture, to simplify the design of a FIFO memory and to reduce manufacture cost. SOLUTION: A comparator 6 compares an input pointer showing a write position into a memory part 2 with an output pointer showing a read position from the memory part 2, and outputs a result signal showing the compared result. An input control part 4 controls the writing of picture data into the memory part 2 by the input pointer and a write permission signal. Then, it masks the write permission signal and inhibits a write operation when the input pointer and the output pointer become equal by the result signal. An output control part 5 controls the reading of picture data from the memory part 2 by the output pointer and the read permission signal. An interruption control part 8 generates an interruption signal showing that the input pointer and the output pointer become equal when it recognizes it by the result signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a first-in-first-out (FIFO) used as a frame buffer of an image processing apparatus.
In particular, the present invention relates to an input / output control circuit of such a FIFO memory.

[0002]

2. Description of the Related Art In an image processing apparatus, image data input from a camera or the like is once stored in a frame buffer and then subjected to internal processing. At this time, a FIFO memory is used as a frame buffer. Here, the write operation frequency (write operation speed) on the input side of the FIFO memory may be different from the read operation frequency (read operation speed) on the output side.

If the write operation speed is faster than the read operation speed, a phenomenon occurs in which the frame data of one frame later is overwritten in the memory section of the FIFO memory before the immediately preceding frame data is read. Such a phenomenon has caused a situation in which frame data, that is, image data, is discontinuous within one frame, which has been a cause of image disturbance called "cut-out".

As the invention for preventing the above-mentioned "cut-out", the following and the following are disclosed.

An invention according to Japanese Patent Application Laid-Open No. 1-282632 (digital image display system) (see FIG. 3)

In FIG. 3, a dual memory (dual-port frame memories A and B) using two dual-port memories corresponds to a FIFO memory.

The invention shown in FIG. 3 has two dual-port frame memories A and B in duplicate, and controls read / write (read and write) of image data input from the image memory to the dual-port frame memories A and B. Are performed alternately, thereby achieving exclusive control of a write operation (write operation) and a read operation (read operation) performed asynchronously. This prevents the image from being disturbed (cut out of the body) caused by overwriting with the next frame data while one frame data (image data) has not been read.

An invention according to Japanese Patent Application Laid-Open No. 7-298089 (frame transmission rate conversion system and method using asynchronous pixel clock) (see FIG. 4)

In FIG. 4, a divided memory (frame buffer) that corrects a shift between writing and reading for each specific number of frames corresponds to a FIFO memory.

The invention shown in FIG. 4 counts the number of frames sent to the display control device by a frame counter, inhibits a write operation (write operation) every time a specific number of frames is processed, and still reads from a frame buffer. To prevent overwriting on existing image data
This is to avoid the body cut.

In these prior arts, the circuit configuration becomes complicated by increasing the number of processed frames or providing a counter (frame counter) for the number of processed frames, thereby increasing the design cost and manufacturing cost. I have. In addition, the invention shown in FIG. 4 lacks versatility because the frame count cannot be determined unless the speed of the write operation to the frame buffer and the speed of the read operation are constant.

[0012]

Conventionally, a FIFO memory in a generally used image processing apparatus has a problem that the phenomenon of "cut-out" occurs as described above.

Further, the prior arts according to the above two publications have the following problems as mentioned above.

The first problem is that, in the method of duplicating the frame memory, the design becomes complicated and the manufacturing cost increases.

The reason for this is that the complexity of the circuit configuration for duplexing and switching the frame memories increases the design difficulty. Also, because the frame memory is duplicated, the circuit scale is increased and the parts cost is increased.

The second problem is that, in the method in which the frame counter is provided, when the writing operation speed and the reading operation speed dynamically fluctuate, it is not possible to eliminate the image cutout.

The reason is that a frame in which existing image data that has not yet been read from the frame buffer is overwritten by input data is calculated from the ratio between the write operation speed and the read operation speed. This is because it is not possible to appropriately cope with a system in which the operation speed fluctuates dynamically.

In view of the above, it is an object of the present invention to provide a FIFO memory which is used as a frame buffer of an image processing apparatus and in which image data write operation and image data read operation are performed asynchronously, the write operation speed and Even when the reading operation speed fluctuates dynamically, existing image data that has not yet been read from the frame buffer during the processing of one frame image (image data) is overwritten by the writing operation. Disorder (short body)
Is to prevent

Another object of the present invention is to eliminate the need for duplicating a frame memory or adding a complicated circuit when realizing the above-mentioned "prevention of body cut". An object of the present invention is to simplify the design and reduce the manufacturing cost of the “FIFO memory to be realized” (small and light weight, high integration, simplified circuit / device configuration, and improved productivity of the FIFO memory).

[0020]

According to the present invention, there is provided a FIFO memory in which an image data write operation and an image data read operation are performed asynchronously, a memory unit for holding one frame of image data, An input pointer indicating a write position to the memory unit is held, and writing of image data to the memory unit is controlled by the input pointer and the write enable signal. When the input pointer and the output pointer become the same, An input control unit that masks the write enable signal and inhibits an operation of writing image data to the memory unit, and an output pointer that indicates a read position from the memory unit. An output control unit for controlling reading of image data from the memory unit, and an input pointer sent from the input control unit A comparator that compares an output pointer sent from the output control unit and outputs a result signal indicating the comparison result, and holds a result signal output by the comparator; and stores the held content in the input control unit. And an interrupt signal indicating that the input pointer and the output pointer become the same based on the result signal output from the comparator and the result signal output from the comparator, and notify the external of the interrupt signal. An interrupt control unit.

[0021]

Next, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an image processing apparatus including an embodiment of a FIFO memory according to the present invention.

This image processing apparatus includes an input image processing unit 1
, The FIFO memory of the present embodiment, the image processing unit 3, and the memory control unit 9.

The input image processing unit 1 converts an external analog image signal into a digital image signal and stores the image data (image data based on the digital image signal) in a FIFO memory.
Supply.

The image processing section 3 processes one frame of image data stored in the FIFO memory.

The memory controller 9 is provided for controlling the FIFO memory.

The FIFO memory of this embodiment holds one frame of image data input from the input image processing unit 1 between the input image processing unit 1 in the preceding stage and the image processing unit 3 in the subsequent stage. Unit 2, input control unit 4, output control unit 5
, A comparator 6, a flip-flop 7, and an interrupt control unit 8 (in FIGS. 1 and 2, the flip-flop is "F / F (Flip / Flo
p) ").

The memory unit 2 is storage means for holding (storing) one frame of image data input to the FIFO memory, and performs a write operation of input data (input image data) and an output data (output image data). ) Is a dual-port memory capable of performing the read operation at the same time as the RAM (Random Access Memory).
ry).

The input control unit 4 controls (holds / updates) an input pointer indicating where in the memory unit 2 the image data input from the input image processing unit 1 is to be written, and controls issuance of a write enable signal.

The output control unit 5 controls (holds / updates) an output pointer indicating where in the memory unit 2 the image data to be sent to the image processing unit 3 is read, and controls issuance of a read permission signal.

The comparator 6 has an input pointer (input control unit 4).
And an output pointer (output pointer sent from the output control unit 5).

The flip-flop 7 is storage means for holding a result signal output as an indication of the result of the magnitude comparison in the comparator 6, and supplies the held result signal to the input control unit 4.

The interrupt control unit 8 generates an interrupt signal based on the result signal output from the comparator 6, and notifies the outside of the FIFO memory (here, the memory control unit 9) of the interrupt signal.

The FIFO memory of this embodiment (portion surrounded by a broken line in FIG. 1) is a one-chip IC (Inte
(Circuited Circuit), and it is desirable to configure such a “one-chip IC shape”.

With the above-described configuration, the FIFO memory of this embodiment and the FIFO memory of the present invention always compares the input pointer for writing the input data and the output pointer for reading the output data with the comparator 6, and compares the input pointer with the input pointer. A state where the output pointer is the same as the output pointer, that is, a state where the existing image data which has not been read from the memory unit yet is overwritten (overwritten) by the input data is detected. And
In response to this detection result, the input control unit 4
By masking the write permission signal for writing to and prohibiting the writing operation, "cut-out" of image data (image) is prevented.

FIG. 2 is a diagram showing a time chart for explaining the operation of the FIFO memory of this embodiment.

Next, the F of the present embodiment thus constructed
The operation of the IFO memory (including the operation of the input image processing unit 1, the image processing unit 3, and the memory control unit 9 relating to the FIFO memory) will be described in detail with reference to FIGS.

First, general operations of the FIFO memory according to the present embodiment are shown in the following (1) to (4).

When a write reset signal (WRST signal) and a read reset signal (RRST signal) are input from the memory control unit 9 to the FIFO memory, each unit in the FIFO memory is initialized.

One frame of image data is input from the input image processing unit 1 to the FIFO memory, and the memory control unit 9 issues a write enable signal (WE signal) to the FIFO memory. The input control unit 4 sends a write permission signal (WE1 signal) to the memory unit 2 and an input pointer indicating a write position (address) of the image data to the memory unit 2, and outputs the image input from the input image processing unit 1. Data memory part 2
Control writing to

When the memory control unit 9 issues a read permission signal (OE signal) to the FIFO memory, the output control unit 5 outputs a read permission signal (OE1 signal) to the memory unit 2 and a read position (address) of image data. Is sent to the memory unit 2 and reading of image data from the memory unit 2 to the image processing unit 3 is controlled.

The input pointer sent from the input control unit 4 and the output pointer sent from the output control unit 5 are compared in magnitude in the comparator 6, and the comparison result is output as a result signal. The result signal is sent to the input control unit 4 via the flip-flop 7. If it is found from the comparison result indicated by the result signal that the input pointer and the output pointer are the same, the input control unit 4 masks the write enable signal (WE1 signal) to the memory unit 2 and disables the write operation. To

At the same time, the result signal is sent to the interrupt control unit 8. Based on the comparison result indicated by the result signal, the interrupt control unit 8 notifies the outside of the FIFO memory (memory control unit 9) that the input pointer and the output pointer have become the same as an interrupt signal (INT signal).

In the write-inhibited state realized by the control of the input control unit 4 in, and the interrupt signal sent out by the interrupt control unit 8, a reset signal is input to the FIFO memory from the outside (input control unit 9). It is released by doing.

Next, a specific operation of the FIFO memory according to the present embodiment will be described with reference to a time chart shown in FIG. Each signal of “OE”, “WE”, and “WE1” in FIG. 2 is “0” as indicated by a bar symbol.
, Each signal is in a state of being “issued (transmitted)”.

First, the operation when the FIFO memory is initialized will be described.

The memory control unit 9 sends out a write reset signal (WRST signal) and a read reset signal (RRST signal) for initializing the FIFO memory.

Upon receiving the WRST signal, the input control unit 4 in the FIFO memory sets the contents of the input pointer indicating the write address to the memory unit 2 to “0000H” (memory unit 2
(The first address of the address) ("H" after the numerical value indicating the address indicates that the numerical value is a hexadecimal number).

Flip-flop 7 and interrupt controller 8
Is also initialized by the WRST signal.

Output control unit 5 receiving the RRST signal
Initializes the contents of the output pointer indicating the read address from the memory unit 2 to "0000H".

Second, one frame of image data is input from the input image processing unit 1, and a write enable signal (WE signal) is sent from the memory control unit 9 (WE signal is "0").
Will be described.

In this case, the input control section 4 sends a write enable signal (WE1 signal) to the memory section 2 to control the write operation of the image data.

For example, in the T0 cycle in FIG. 2, the WE1 signal based on the WE signal and the value of the input pointer “1233H” cause the writing operation of the image data to the area of the address “1233H” in the memory unit 2 to be performed. Done.

When such a write operation is completed, the input control unit 4 updates the value of the input pointer held by itself.

For example, the address indicated by the input pointer is updated from the address "1233H" to the next address "1234H" between the T0 cycle and the T1 cycle in FIG. 2. In the T2 cycle, the address of the image data to the address "1234H" is updated. A write operation is performed.

Third, the operation in the case where a read permission signal (OE signal) is transmitted from the memory control unit 9 (the OE signal becomes “0”) will be described.

In this case, the output control section 5 sends a read permission signal (OE1 signal) to the memory section 2 and controls reading of image data in the memory section 2.

For example, in the T0 cycle in FIG. 2, the read operation of the image data from the area of the address "1234H" in the memory unit 2 is performed by the OE1 signal based on the OE signal and the value of the output pointer "1234H". Done.

Fourth, an operation when there is a possibility that unread data may be overwritten by input data from the input image processing unit 1 when unread data exists in the memory unit 2 will be described.

For example, in FIG. 2, when data is read from address "1234H" in cycle T0, the output pointer is updated to "1235H".

On the other hand, in the T2 cycle, the address “1234”
When the image data is written to "H", the input pointer is updated to "1235H".

Here, in the T3 cycle, the comparator 6
Performs a magnitude comparison between the input pointer and the output pointer, and as a result signal indicating the comparison result, “0” (information indicating that the input pointer and the output pointer are the same).
Is output.

In response to the result signal, the content stored in the flip-flop 7 becomes “0” in the cycle T 4, and the result signal is sent to the input control unit 4.

In this state, even if the memory controller 9 issues a next data write instruction (transmission of a write enable signal (WE signal)) in the T4 cycle, the content of the flip-flop 7 is set to "0". Therefore, the output control unit 5 does not issue the write enable signal (WE1 signal). That is, the WE1 signal is masked based on the content of "0" of the flip-flop 7, and the value of "1" is maintained.

Therefore, in the memory section 2, unread data is not overwritten by the next input data. This can prevent the image from being cut off.

In the T3 cycle, the result signal is set to "0".
Is sent to the interrupt control unit 8, the interrupt signal (INT signal) becomes "1" in the T4 cycle, and the memory control unit 9 (outside of the FIFO memory) is notified that the write inhibit state has occurred.

The memory control unit 9 interrupts the input of the image data from the input image processing unit 1 based on the interrupt signal, sends out the WRST signal after the output of the unread data is completed, and interrupts the input of the image data. First from the beginning of the data
The input of the image data for the frame is redone.

[0068]

As described above, according to the present invention, the following effects are produced.

The first effect is that unread data in the FIFO memory is not overwritten by new input data. As a result, it is possible to prevent the phenomenon that the output image is disturbed (cut body).

The reason why such an effect occurs is that the input pointer is compared with the output pointer, and when the input pointer and the output pointer are the same, the write enable signal is masked and the write operation to the FIFO memory is prohibited. Because you can do it.

The second effect is that, when the first effect is realized, it is not necessary to adopt a complicated circuit configuration, the complexity of the design can be eliminated, and the manufacturing cost does not increase. That's what it means.

The reason for such an effect is that the entirety of the FIFO memory of the present invention can be formed by components having a relatively simple structure (for example, the FIFO memory of the present invention).
This is because the entire memory can be realized by one IC), so that the amount of control circuits around the FIFO memory can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration and the like of an embodiment of a FIFO memory according to the present invention.

FIG. 2 is a diagram showing a time chart for explaining the operation of the FIFO memory shown in FIG. 1;

FIG. 3 is a block diagram for explaining an example of a conventional FIFO memory.

FIG. 4 is a block diagram for explaining another example of a conventional FIFO memory.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Input image processing part 2 Memory part 3 Image processing part 4 Input control part 5 Output control part 6 Comparator 7 Flip-flop (F / F) 8 Interrupt control part 9 Memory control part

Claims (3)

[Claims] 1. A FIFO memory in which an operation of writing image data and an operation of reading image data are performed asynchronously, a memory unit for holding one frame of image data, and an input pointer indicating a writing position in the memory unit. And controlling the writing of the image data to the memory unit by the input pointer and the write enable signal. When the input pointer and the output pointer become the same, the write enable signal is masked to the memory unit. An input control unit for prohibiting the writing operation of the image data, and an output pointer indicating a reading position from the memory unit, and reading of the image data from the memory unit is controlled by the output pointer and the read permission signal. An output control unit; an input pointer sent from the input control unit; and an output pointer sent from the output control unit. A comparator that outputs a result signal indicating the result of the comparison, a flip-flop that holds the result signal output by the comparator, and supplies the held content to the input control unit; And an interrupt control unit for generating an interrupt signal indicating that the input pointer and the output pointer are the same based on the result signal output from the device and notifying the interrupt signal to the outside. FIFO memory. 2. The FIFO memory according to claim 1, wherein image data is input from an input image processing unit, image data is output to the image processing unit, and the FIFO memory operates under the control of a memory control unit. 3. The FIFO memory according to claim 1, wherein the FIFO memory is configured to have a one-chip IC shape.