JP2000287180A - Video data processing unit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To change a write control function of a write control section within a prescribed time after a setting change even when a received vertical synchronizing signal is intermittent. SOLUTION: The video data processing unit where a write control function of a write control section 12 is changed by changing a setting value S, is provided with a means that generates a 1st timing signal (5) when the setting value S is changed, a quaternary counter 32 that uses the signal (5) for a reset signal to count an output vertical synchronizing signal (6), and an OR circuit 34 that ORs a carry signal (7) of the quaternary counter 32 and an input vertical synchronizing signal (8) and provides an output of the ORed signal as a capture signal of the setting value S. When the setting value S is changed when the signal (8) is intermittent, the signal (5) resets the quaternary counter 32, which starts counting the signal (6) and provides an output of a signal (7) when the count reaches '3'. Since this signal (7) becomes a capture signal of the setting value S, the write control function of the write control section is changed into a function corresponding to the setting value S after it is revised.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention comprises a frame memory, a write control unit for controlling writing of video data to the frame memory, and a read control unit for controlling reading of video data to the frame memory. The present invention relates to a video data processing device capable of changing a write control function of the write control unit by changing a set value S taken in based on a vertical synchronization signal.

[0002]

2. Description of the Related Art Generally, in a video data processing device using a frame memory, a function for controlling writing and reading of video data to and from the frame memory is written with a write control function so that the video is not disturbed when the setting is changed. This is performed in synchronization with a vertical synchronization signal of video data (hereinafter, simply referred to as an input vertical synchronization signal), and the read control function is synchronized with a vertical synchronization signal of video data to be read (hereinafter, simply referred to as an output vertical synchronization signal). Do.

Conventionally, this kind of video data processing apparatus is shown in FIG.
It was configured as shown. That is, the frame memory 10, the write control unit 12, the read control unit 14, the C
PU (central processing unit) 16, first register 18, and second register 18
The writing control unit 12 includes a register 20, and stores a frame of input video data in the frame memory 10 based on the input horizontal synchronizing signal and vertical synchronizing signal. Can change the write control function. The read control unit 14 outputs a read control signal to the frame memory 10 based on the input vertical synchronization signal and the timing signal input from the CPU 16 to read video data from the frame memory 10 and output the read video signal to the display unit. And outputs a horizontal synchronization signal and a vertical synchronization signal whose start timing is synchronized with the read control signal to the display unit side.

The CPU 16 generates a set value S by inputting or taking in data corresponding to the set value S, and outputs the set value S to the first register 18, and the second register 20 transmits the set value from the first register 18 by an input vertical synchronization signal. S is fetched and output to the write control unit 12, and the write control function is set to a corresponding function. When the set value S generated by the CPU 16 and output to the first register 18 is changed, the set value S output from the second register 20 to the write control unit 12 is also changed. The control function is changed.

[0005]

However, in the conventional example shown in FIG. 4, if the input vertical synchronizing signal for taking the set value S into the write control unit 12 is interrupted, the write control function cannot be changed. There was a problem. That is, even if the CPU 16 generates a new set value S and outputs it to the first register 18, if the input vertical synchronization signal is interrupted, it is not taken into the second register 20, and the new set value S is input to the write control unit 12. Therefore, the write control function is not changed until the input vertical synchronization signal is input again. The present invention has been made in view of the above-described problems, and provides a video data processing apparatus capable of changing a write control function of a write control unit within a predetermined time after a change of a set value S even when an input vertical synchronization signal is interrupted. It is intended to do so.

[0006]

The present invention comprises a frame memory, a write controller for controlling writing of video data to the frame memory, and a read controller for controlling reading of video data to the frame memory. , A set value S taken in based on an input vertical synchronization signal
In the video data processing device capable of changing the write control function of the write control unit by changing the timing, a timing signal generating means for generating a first timing signal when the set value S is changed, and a first timing generated by the timing signal generating means An N-ary counter for counting the vertical synchronization signal output from the read control unit using the signal as a reset signal, a logical sum signal of the carry signal and the input vertical synchronization signal output from the N-ary counter, and a set value S to the write control unit. A logical sum circuit that outputs the signal as a signal to be taken in.

When the set value S is changed when the input vertical synchronizing signal is interrupted, the first timing signal generated by the timing signal generating means when the set value S is changed resets the N-ary counter, and the N-ary counter Starts counting the vertical synchronization signal output from the read control unit, and outputs a carry signal when the count value of the N-ary counter reaches N−1,
Since the carry signal is output as a signal for capturing the set value S, the changed set value S is captured by the write control unit, and the write control function is changed.

When the input vertical synchronizing signal is normally input without interruption, the set value S is synchronized with the input vertical synchronizing signal.
Is set to be longer than the period of the input vertical synchronizing signal from the time when the N-ary counter is reset until the time when the carry signal is output.

In order to eliminate the influence of the delay of the data processing time by the control means, a first register for immediately storing the changed set value S, and a set value S stored in the first register for the logical sum circuit. And a second register which receives the output signal and outputs it to the write control unit.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a video data processing apparatus according to the present invention will be described below with reference to FIG. In FIG. 1, the same parts as those in FIG. In FIG. 1, reference numeral 10 denotes a frame memory for storing one frame of video data, 12 denotes a write control unit, 14 denotes a read control unit, 18 denotes a first register, 20 denotes a second register, and 30 denotes a second register.
Is a CPU (Central Processing Unit), 32 is a quaternary counter as an example of an N-ary counter, and 34 is a logical sum circuit.

The writing control unit 12 stores one frame of input video data in the frame memory 10 based on the input horizontal synchronizing signal and vertical synchronizing signal, and performs a writing control function by changing the set value S. Can be changed. The read control unit 14 outputs a read control signal to the frame memory 10 based on an input vertical synchronization signal and a timing signal input from the CPU 30, and outputs a horizontal synchronization signal whose start timing is synchronized with the read control signal. The vertical synchronization signal is output to the display.

The CPU 30 has a ROM (not shown).
A function of generating a set value S by inputting or taking in data corresponding to the set value S, and outputting the generated data to the first register 18 as in the conventional example, by executing a program stored in the (read only memory). In addition to the function of generating a timing signal and outputting it to the read control unit 14, it has the following functions (a) and (b). (A) A function of detecting a change in the set value S and generating a signal as a first timing signal when the set value S is changed. (B) a function of detecting a change in the set value S and generating a signal as a second timing signal when the set value S is changed. The signal generated by the function (a) is input to the CLR (clear) terminal of the quaternary counter 32 as a clear signal. The signal generated by the function (b) is input to the first register 18 as a capture signal immediately after the signal generated by the function (a).

The quaternary counter 32 is provided with the CPU 30
Reset by the clear signal output from
The vertical synchronization signal output from the read control unit 14 is counted, and when the count value reaches “3”, a carry signal is output. The OR circuit 34 includes the write control unit 1.
The logical sum signal of the vertical synchronizing signal input to 2 and the carry signal output from the quaternary counter 32 is output to the second register 20. The first register 18 stores a set value S (data) output from the CPU 30 by a capture signal output from the CPU 30, and the second register 20 stores a logical sum signal output from the logical sum circuit 34. The set value S (data) set in the first register 18 is fetched as a fetch signal, and is output to the write control unit 12 as the set value S (data).

Next, the operation of FIG. 1 will be described with reference to FIGS. 2 and 3. A: First, when the set value S is changed from “n” to “n + α” to change the write control function using FIG. 2, the input vertical synchronization signal is normal as shown in FIG. 2 (i). The case in which is input to is described. It is assumed that a normal vertical synchronizing signal is output from the read control unit 14 as shown in FIG.

(1) The CPU 30 sets a new set value “n +
The set value “n + α” is created by inputting or taking in data corresponding to “α”, and is output as data from the CPU 30 at the timing shown in FIG. 2A, and at the timing shown in FIGS. And outputting signals as first and second timing signals.

(2) The CPU 30 receives the signal as a capture signal.
To the first register 18, the set value “n + α” is set as data in the first register 18 at the timing shown in FIG.

(3) When the signal is input to the CLR terminal of the quaternary counter 32 as a clear signal to reset the quaternary counter 32, the quaternary counter 32
2 starts counting vertical synchronization signals output from
The count value K changes at the timing shown in FIG. When the count value K of the quaternary counter 32 reaches "3", FIG.
The carry signal is output from the carry terminal as shown in FIG. The period T from the time when the quaternary counter 32 is reset to the time when the carry signal is output is set to be longer than the period of the input vertical synchronization signal.
There are two input vertical sync signals. In this embodiment, as shown in FIGS. 2H and 2I, three input vertical synchronizing signals exist in the period T.

(4) The set value "n + α" set in the first register 18 appears immediately after the signal shown in FIG. 2D, and appears immediately after the signal shown in FIG. 2J. This corresponds to the input vertical synchronizing signal.) And is taken into the second register 20, and the changed set value “n + α” is input to the write controller 12 as data at the timing shown in FIG. Be changed.

B: Next, referring to FIG. 3, the set value S is changed from “n” to “n +” in order to change the write control function.
When the input vertical synchronization signal is changed to
A case where the signal is interrupted (L level signal is continued) as shown in (i) will be described. Read control unit 14
After that, it is assumed that a normal vertical synchronization signal is output as shown in FIG.

(1) The CPU 30 sets a new set value “n +
A set value “n + α” is created by inputting or taking in data corresponding to “α”, and is output as data from the CPU 30 at the timing shown in FIG. 3A, and at the timing shown in FIGS. And outputting signals as first and second timing signals.

(2) The CPU 30 receives the signal as a capture signal.
To the first register 18, the set value “n + α” is set as data in the first register 18 at the timing shown in FIG.

(3) When the signal is input to the CLR terminal of the quaternary counter 32 as a clear signal to reset the quaternary counter 32, the quaternary counter 32
Starts counting the vertical synchronization signal output from the
The count value K changes at the timing shown in FIG. When the count value K of the quaternary counter 32 reaches “3”, FIG.
The carry signal is output from the carry terminal as shown in FIG.

(4) The set value "n + α" set in the first register 18 is the second register at the rising edge of the signal shown in FIG. 3 (j) (corresponding to the signal passed through the OR circuit 34). 20 and the changed set value "n +
“α” is input to the write control unit 12 as data at the timing shown in FIG. 10C, and the write control function is changed.

In the embodiment, when the input vertical synchronizing signal is normally input without interruption, the set value S can be taken into the write control unit in synchronization with the input vertical synchronizing signal. For this reason, the case where the period T from the reset of the N-ary counter to the output of the carry signal is set to be longer than the period of the input vertical synchronization signal has been described, but the present invention is not limited to this, and the present invention is not limited to this. The present invention can also be used when the period T from the time to the output of the carry signal is set shorter than the period of the input vertical synchronization signal. In this case, as in the case where the input vertical synchronizing signal is interrupted, the setting value may not be taken into the write control unit in synchronization with the input vertical synchronizing signal. Since the control function can be changed, the image is not extremely disturbed when the setting is changed.

In the above embodiment, in order to eliminate the influence of the delay of the data processing time by the control means, the first register for immediately storing the changed set value S, and the set value stored in the first register A case has been described in which a second register is provided for receiving S with the output signal of the OR circuit and outputting the same to the write control unit. However, the present invention is not limited to this, and one or both of the first and second registers are provided. Can be used even when is omitted.

[0026]

According to the present invention, there is provided a video data processing apparatus comprising a frame memory, a write control section and a read control section, wherein the write control function of the write control section can be changed by changing the set value S taken in based on the input vertical synchronization signal. In the apparatus, a timing signal generating means for generating a first timing signal when the set value S is changed, an N-ary counter for counting a vertical synchronizing signal output from the read control unit using the first timing signal as a reset signal, An OR circuit for outputting a logical sum signal of the carry signal output from the N-ary counter and the input vertical synchronizing signal as a signal for taking in the set value S to the write control unit; The N-ary counter is reset by the timing signal, and the count value of the vertical synchronization signal by the N-ary counter becomes N-1.
, The carry signal output when the set value S is reached is output to the write control unit as a signal for capturing the set value S. Therefore, even if the input vertical synchronizing signal is interrupted, the carry signal is output within a certain period of time after the change of the set value S. The write control function can be changed by taking the set value S into the write control unit.

If the period T from the resetting of the N-ary counter to the output of the carry signal is set longer than the period of the input vertical synchronizing signal, when the input vertical synchronizing signal is normally input without interruption, The set value S can be taken into the write control unit in synchronization with the input vertical synchronization signal,
It is possible to prevent the image from being disturbed when the setting is changed.

There is provided a first register for immediately storing the changed set value S, and a second register for receiving the set value S stored in the first register with an output vertical synchronizing signal and outputting it to the read control unit. In this case, the influence of the delay in the data processing time by the control means can be eliminated.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a video data processing device according to the present invention.

FIG. 2 is a timing chart for explaining an operation when an input vertical synchronizing signal for taking in a set value S in FIG. 1 is normally input;

FIG. 3 is a timing chart illustrating an operation when an input vertical synchronization signal for taking in a set value S in FIG. 1 is interrupted;

FIG. 4 is a block diagram showing a conventional example.

[Description of Signs] 10: Frame memory, 12: Write control unit, 1
4 readout control unit, 18 first register, 20 second register, 30 CPU, 32 quaternary counter (an example of N-ary counter), 34 OR circuit,
... Data representing the set value S,... Fetch signal,... Clear signal,.

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Kenji Shimura 1116 Suenaga, Takatsu-ku, Kawasaki-shi, Kanagawa F-term in Fujitsu General Limited (reference) 5C053 FA27 HC01 JA27 JA28 KA03 KA05 KA20 KA21 KA24

Claims (3)

[Claims] A frame memory; a write control unit for controlling writing of video data to the frame memory; and a read control unit for controlling reading of video data to the frame memory, based on an input vertical synchronization signal. A video signal processing device capable of changing a write control function of the write control unit by changing a set value S to be read in, a timing signal generating means for generating a first timing signal when the set value S is changed; An N-ary counter for counting the vertical synchronization signal output from the read control unit using the first timing signal generated by the means as a reset signal, and a logical sum signal of the carry signal output from the N-ary counter and the input vertical synchronization signal. A signal for taking the set value S into the write control unit. Video data processing apparatus characterized by comprising; and a logical sum circuit which outputs. 2. The video data processing apparatus according to claim 2, wherein a period T from the time of reset to the time of output of the carry signal of the N-ary counter is set to be longer than the cycle of the input vertical synchronization signal. 3. The timing signal generating means outputs a second timing signal immediately after outputting a first timing signal output when the set value S is changed, and uses the second timing signal as a set signal as a set value. A first register for setting
3. The video data processing according to claim 1, further comprising: a second register that takes in the set value S stored in the first register with an output signal of the OR circuit and outputs the set value S to the write control unit as the set value S. apparatus.