JP3509658B2 - Operation mode switching circuit and method - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an operation mode switching circuit and method thereof, and more particularly to a read operation mode in a memory device in which a write control circuit writes data to a buffer memory while a read control circuit reads data. Of the switching circuit.

[0002]

2. Description of the Related Art MPEG2 (MOVING PICTURE EXPERTS G
ROUP PHSE 2) etc., in the processing system of image compression data,
When the output data from the encoding device for image compression is written to the buffer memory and then the data is read from this buffer memory at a rate different from the write rate, the read operation for the read side of the memory The mode setting is specified by a data processing device such as a CPU.

Generally, in an apparatus such as MPEG2, a GOP (GROUP) generated in an encoding apparatus is used.
OF PICTURES) Generate a signal with the same timing as a synchronization signal such as synchronization, input the output signal to the CPU, and
Based on the timing, the PU changes the operation mode necessary for compression processing, such as the bit rate on the encoding device side. As described above, when the encoded output, which is the output of this encoding device, is read while writing to the buffer memory, the operation mode on the reading side can also be changed based on the mode setting information for the writing operation to the memory by the CPU. Done.

Here, the synchronizing signal for GOP synchronization will be described. In the image compression processing, an image is divided into a plurality of groups (for example, divided into groups of 15 frames), and therefore, the encoding apparatus is used. Header information indicating the beginning of the group is inserted in the output data of, and a signal indicating the insertion position of this header information is called a GOP synchronization signal.

[0005]

Conventionally, when the operation mode on the read side of the memory is changed, a header detection circuit for detecting header information on the read side is provided, and the CP
There is a method of changing the read operation mode according to the header timing on the read side by the mode setting information by U.
According to this method, when the header information is input more than once on the writing side and then the header is read for the first time on the reading side (this phenomenon occurs because the reading rate is slower than the writing rate). A situation occurs in which the mode cannot be changed from the correct header timing on the read side.

There is also a method in which the CPU manages both the data on the write side and the data on the read side of the memory and changes the operation mode on the read side at the header timing of the read data that matches the change timing on the operation mode on the write side. However, this method has a drawback in that the load on the CPU is unnecessarily large.

An object of the present invention is to provide an operation mode switching circuit capable of reducing the load on the CPU and accurately changing the operation mode on the reading side.

[0008]

According to the present invention, there is provided a read operation mode switching circuit in a memory device in which a write control circuit writes data to a buffer memory and a read control circuit reads data. Write address storage means for storing the write address of the buffer memory in response to the change timing of the read operation mode designated from the outside, and the read operation when the stored write address and read address match. An operation mode switching circuit is obtained which includes mode switching control means for instructing the read control circuit to change the operation mode.

The data is a plurality of groups of data with header information added to the head of each group, and the change timing is detected in synchronization with the header timing indicating the position of the header information. It is characterized in that it includes mode change detection means, and the write address storage means stores the write address at the time of the change timing.

Further, the mode switching control means stores the read operation mode at the time of the change timing, compares the storage write address with the read address, and responds to the coincidence detection by the comparison. And a means for outputting the read operation mode stored as above to the read control circuit.
The change of the read operation mode is a change of the read data amount per unit time.

According to the present invention, there is provided a method of switching a read operation mode in a memory device, wherein a write control circuit writes data to a buffer memory and a read control circuit reads data, which is designated from the outside. A write address storing step of storing a write address of the buffer memory in response to a change timing of the read operation mode, and the change of the read operation mode when the stored write address and read address match. And a mode switching control step for instructing the read control circuit.

The data is a plurality of groups of data with header information added to the head of each group, and the change timing is detected in synchronization with the header timing indicating the position of the header information. It is characterized in that it includes a mode change detecting step, and the write address storing step stores the write address at the time of the change timing.

The mode switching control step includes
The step of storing the read operation mode at the time of the change timing, the step of comparing the storage write address with the read address, and the read control of the read operation mode stored in response to the match detection by the comparison. Outputting to a circuit.

The operation of the present invention will be described. Based on the information that the operation mode on the write side of the buffer memory has been switched, the operation mode switched on the write side in synchronization with the header detection timing and the memory write address at that time are stored. Then, when the memory read address matches the stored write address, the operation mode switched is instructed to the read side. This makes it possible to change the operation mode setting for the read side immediately from the data that has changed the mode setting.
It is possible for the CPU to change the mode setting without considering the operation timing on the reading side.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a memory device used in a compressed data processing system to which a mode switching circuit 15 according to an embodiment of the present invention is applied. In FIG.
The encoding device 10 encodes image data (not shown), and the CPU 11 controls the operation of the encoding device and also generates mode setting data for setting an operation mode. The sync signal generator 12 is for generating various sync signals.

The encoding device 10 uses the encoded data IN
When DT is output and only a part of valid transfer data exists in the transfer area, strobe signal STRB1 is added so that valid data can be discriminated. still,
CLK1 is the transfer clock at the encoder output.

The CPU 11 controls the encoding device 10 and sets the mode for the write / read operation of the memory 16 based on the timing information from the synchronization signal generator 12. The header detection circuit 13 detects a header (GOP synchronization), which is a starting point for changing the mode setting, from the data output from the encoding device 10, sends the header timing to the mode switching circuit 15, and outputs the input data IN.
The DT is output as the write data WRDT to the memory 16.

The write controller 14 generates a write address WRAD for the memory 16, a write clock WCK, and a write enable signal WEN. The mode switching circuit 15 receives the mode setting data 1 from the CPU 11,
Further, the header detection circuit 13 receives the header timing which is the start point of the mode setting change on the writing side. Further, the write address and the read address RDAD are respectively received from the write controller 14 and the read controller 17, and the mode setting data on the read side is switched based on these information.

The read controller 17 generates a read address, a read enable signal REN, and further a data read signal such as a read clock RCK for the memory 16 when there is a data transfer request REQ from the host device. . The upper device 18 sends a data transfer request and a transfer clock CLK2 to the read controller 17, and
It receives and processes the data RDDT read from the memory.

FIG. 2 shows the mode switching circuit 15 shown in FIG.
It is a block diagram which shows one Example. In FIG. 2, the mode change detection circuit 2 includes the header timing from the header detection circuit 13 and the mode setting data 1 from the CPU 11.
Based on (information that the writing mode has been switched),
On the write side, a timing 1 for storing the address where the mode setting start data is written in the write address WRAD fetch device 3 is generated.

The write address fetch unit 3 stores the write address WRAD at this timing 1, and the comparison circuit 4 compares the stored write address and read address, and when they match, generates the timing 2. And outputs it to the setting data fetching device 5. The setting data fetching device 5 fetches the mode setting data 1 in synchronization with the timing 1 from the mode change detecting circuit 2 (mode setting data 2), and fetches the fetching mode setting data 2 in synchronization with the timing 2 from the comparing circuit 4. , Mode setting data 3 is output to the read controller 17.

The operation of the embodiment of the present invention will be described below with reference to the flowchart of FIG. 3 and the timing chart of FIG. Note that the reference numerals of the signals in the time chart of FIG. 4 are the same as those of the signals of FIGS. 1 and 2. CLK1 is a transfer clock from the encoding device 10, and INDT is output data from the encoding device 10. In this data, "S" is a pseudo representation of the synchronization signal (header information) to be detected. Although "S" is shown with one clock width, there is no problem even if it actually has several clock widths.

STRB1 is a flag indicating valid data in INDT. Here, it is assumed that the data is valid when it is low. SEQ-HEAD indicates the header timing in the header detection circuit 13. Here, when it is low, it indicates that it is header data. The CPU 11 wants to switch the mode on the write side in the header when the write address WRAD is "L" and sets the mode setting data 1 to "
Change from "A" to "B".

Timing 1 is whether or not SEQ-HEAD is low and, when SEQ-HEAD is low, the immediately preceding SEQ-HEAD.
In the section where is low, it is judged whether or not the mode setting data has been changed (step S1), and if this condition is met, the SEQ-HEAD is set to the same width as the low section (low / high). The distinction depends on the system).

The memory write address WRAD when the timing 1 is low is held by the write address fetch unit 3 as the fetch address on the write side (step S2).
3). The mode is changed on the writing side from the data written in this address. In the case of this example, the address is "L". At the timing of holding the address, the mode setting data is also held as the mode setting data 2 in the setting data fetching device 5 in the same manner as the write address (step S3).

CLK2 is a memory read clock.
There is no problem if the cycle is different from CLK1. The read address RDAD, which increases every time data is read, is monitored (step S4), and when the read address RDAD becomes "L" (step S5), the mode setting data 3 is set to change the mode. Take in the value of mode setting data 2. By supplying the value of the mode setting data 3 as it is to the read controller 17 which is a circuit on the read side (step S6) and using it, the value is written to the address "L" on both the write side and the read side. The mode can be changed from the data.

FIG. 5 is an enlarged view of a part of the timing chart of FIG.
An example in which the read operation is different is shown. That is, in this example, in the mode A, the reading is performed only during the X period of the time width 5X, but when the read address RDAD becomes L, the reading is performed during the 3X period. That is, the read data amount per unit time is changed.

In this embodiment, the idea of timing adjustment by a delay element such as a flip-flop is not incorporated, but in designing an actual circuit, it is necessary to add a delay element or the like in accordance with the performance of the device or the like. It is clear that there is.

FIG. 6 is a block diagram of another embodiment of the present invention, in which the same parts as in FIG. 1 are designated by the same reference numerals. In the example of FIG. 1 described above, as the buffer memory, an address such as SRAM is given to read / write data.
This is an example of a memory such as a line memory, a line memory, and a field memory that can read and write without an address.

Also in this configuration, in addition to applying the reset signal RESET to the write controller 14 and the read controller 17, the reset signal RESE is also applied to the memory 16.
By applying T 1 at a common timing, the same effect as in the embodiment of FIGS. 1 and 2 can be obtained.

In this example, the memory 16 can be written and read without an address, but the write controller 1
4 and the read controller 17, it is necessary to generate and send signals WRAD and RDAD corresponding to them to the mode switching circuit 15. Therefore, the write controller 14 is provided with a counter (not shown) for counting the write clock CLK1, and the read controller 17 is provided with a counter (not shown) for counting the read clock CLK2.
These counter outputs are used as WRAD and RDAD, and these counters are reset by the reset signal RESET to the memory 16
At the same time, it should be reset.

[0032]

As described above, according to the present invention, the operation mode on the read side can be changed accurately and immediately at the change header timing of the operation mode on the write side without burdening the CPU.
The effect is that they can be switched.

[Brief description of drawings]

FIG. 1 is a block diagram of a memory device using an operation mode switching circuit according to an exemplary embodiment of the present invention.

FIG. 2 is a block diagram of an operation mode switching circuit according to an embodiment of the present invention.

FIG. 3 is a flowchart showing the operation of the embodiment of the present invention.

FIG. 4 shows the operation of the embodiment of the present invention.

5 is a partially enlarged view of the timing chart of FIG.

FIG. 6 is a block diagram for explaining another embodiment of the present invention.

[Explanation of symbols]

2 Mode change detection circuit 3 Write address capture device 4 Comparison circuit 5 Setting data importer 10 Encoding device 11 CPU 12 Synchronous signal generator 13 Header detection circuit 14 Light controller 15 mode switching circuit 16 haffa memory 17 Lead controller 18 Upper device

Front page continuation (58) Fields surveyed (Int.Cl. ⁷ , DB name) G06T 1/00-1/60 H04N ⁷ /24-7/68 G11C ⁷ /00-7/24 G06F 5/06

Claims (8)

(57) [Claims] 1. A read operation mode switching circuit in a memory device in which a write control circuit writes data to a buffer memory while a read control circuit reads data, and the read operation is specified from the outside. Write address storage means for storing a write address of the buffer memory in response to a mode change timing, and a change of the read operation mode to the read control circuit when the stored write address and read address match. An operation mode switching circuit including a mode switching control means for instructing. 2. The data is a plurality of groups of data with header information added to the beginning of each group, and the change timing is detected in synchronization with a header timing indicating the position of the header information. 2. The operation mode switching circuit according to claim 1, further comprising mode change detection means, wherein the write address storage means stores the write address at the time of the change timing. 3. The mode switching control means, means for storing the read operation mode at the time of the change timing, means for comparing the stored write address and the read address, and response to coincidence detection by this comparison. 3. The operation mode switching circuit according to claim 2, further comprising means for outputting the read operation mode stored as described above to the read control circuit. 4. The operation mode switching circuit according to claim 1, wherein the change of the read operation mode is a change of a read data amount per unit time. 5. A method of switching a read operation mode in a memory device, wherein a write control circuit writes data to a buffer memory and a read control circuit reads data, the read operation being specified from the outside. A write address storing step of storing a write address of the buffer memory in response to a mode change timing, and a change of the read operation mode to the read control circuit when the stored write address and read address match. And a mode switching control step for instructing. 6. The data is a plurality of groups of data with header information added to the head of each group, and the change timing is detected in synchronization with a header timing indicating the position of the header information. 6. The operation mode switching method according to claim 5, further comprising a mode change detecting step, wherein the write address storing step stores the write address at the time of the change timing. 7. The mode switching control step includes a step of storing the read operation mode at the time of the change timing, a step of comparing the stored write address and the read address, and a response to coincidence detection by the comparison. 7. The operation mode switching method according to claim 6, further comprising the step of outputting the read operation mode stored as described above to the read control circuit. 8. The operation mode switching method according to claim 5, wherein the change of the read operation mode is a change of the read data amount per unit time.