JP2002034002A - Image-synchronizing method and recording and regenerating apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize optimum data compression processing by controlling the bank processing of memory for performing MPEG processing, without having to install a storage device individually to a non-standard signal of an analog image signal or the like. SOLUTION: In a recording and reproducing apparatus which records and regenerates an image digital signal, an image input signal is synchronized with an internal system of the recording and reproducing apparatus, by measuring the frame period of the input image signal with a reference clock, and making the write bank of an MPEG compression processing memory for performing proper MPEG compression processing according to the frame period by causing frame skipping or repeating.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video synchronizing method and an MPEG (moving image compression) method used when recording and reproducing a video signal and an audio signal using data compression processing based on MPEG (moving image compression standard) or the like. The present invention relates to a recording / reproducing apparatus having a built-in data compression processing means based on (standard).

[0002]

2. Description of the Related Art A home VTR not synchronized with a system
If the MPEG processing is performed on a reproduced video signal such as a video signal of 8 mm tape video movie or the like, frames may be overtaken or overtaken, and accurate data compression processing may not be performed. In order to solve this, it is necessary to synchronize the input data with the system. This includes:
It is called a frame synchronizer. For example, by writing video data with a clock synchronized with an input reproduced video signal (non-standard video signal) and reading the video data from a frame memory with a reference signal generated with a reference clock, a non-standard signal ( There is a method of converting an input signal into a standard signal (synchronous with the system) and then performing MPEG processing. The basic operation of the frame synchronizer will be described with reference to the timing charts of FIGS. 8 and 9 and the configuration diagram of FIG.

FIG. 10 shows a conventional frame synchronizer that converts a non-standard signal into a standard signal and converts the non-standard signal into an MPEG signal.
FIG. 9 is a configuration diagram for performing an encoding process. 18 is an A / D conversion circuit, 19 and 21 are frame memories, 20 is a frame synchronizer, 22 is an MPEG encoder,
3 is a CPU circuit, 24 is an MPEG decoder, 25 is D
/ A conversion circuit. As shown in the figure, frame memories 19 and 21 are separately required for the frame synchronizer 20 and the MPEG encoder 22.

In FIGS. 8 and 9 of the timing charts, the timing charts are schematically shown (with large periodic fluctuations which are normally impossible) for easy understanding.

[0005] Normally, the frame synchronizer 20 uses a corresponding frame memory 19 to change the clock or synchronization timing, thereby converting a non-standard signal or a signal with jitter into a standard signal, and converting the data into a reference frame period. Output in synchronization with. The input and output of the frame synchronizer 20 are completely asynchronous, and there is a case where the input overtakes or overtakes the output by one frame in a certain cycle. Therefore, in order to adjust this, it is necessary to repeat one frame data or to skip one frame data at the time of output of the frame synchronizer 20.

In FIG. 8, an external input synchronization signal (Xpst
_E) indicates the timing when the period is somewhat longer than the internal reference synchronization signal (Xpst_i). In this case,
When the phase difference between the external input synchronizing signal (Xpst_e) and the internal reference synchronizing signal (Xpst_i) becomes equal to or less than 0 frame, a process of reading the previous frame again is performed. FIG. 8 is a diagram in which frame 2 (f2) is repeated.

In FIG. 9, an external input synchronization signal (X
pst_e) indicates the timing when the period is somewhat shorter than the internal reference synchronization signal (Xpst_i). In this case, the phase difference between the external input synchronization signal (Xpst_e) and the internal reference synchronization signal (Xpst_i) is one frame or more. If so, the next frame is skipped. FIG.
Is a diagram in which the frame 4 (f4) is skipped.

[0008]

When a recording / reproducing apparatus equipped with an encoder such as MPEG records an external input signal (including a non-standard signal), synchronization is performed by a frame synchronizer or the like as described above. But in this case,
A separate frame memory is required for the frame synchronizer, which leads to an increase in cost. The present invention does not provide a separate frame memory for non-standard signals,
An object of the present invention is to provide a video synchronization method capable of standardizing a non-standard signal simply and at low cost by controlling a frame memory for performing an MPEG encoding process and performing a good MPEG encoding process.

[0009]

According to a first aspect of the present invention, in a recording / reproducing apparatus for recording / reproducing a video digital signal, a frame cycle of an input video signal is measured with a reference clock, and the frame rate is determined in accordance with the cycle. This is a video synchronization method characterized by synchronizing an input video signal with an internal system of the recording / reproducing apparatus by skipping or repeating a writing bank of an MPEG compression processing memory for performing an MPEG compression process.

According to a second aspect of the present invention, in the first aspect, when a frame period of the input video signal is longer than a reference frame period by a specified range or more, reading of a frame bank of the memory for MPEG compression processing is repeated. A video synchronization method characterized in that when the frame period of a video signal is shorter than a reference frame period by a specified range or more, reading of a frame bank of a memory for MPEG compression processing is skipped.

According to a third aspect of the present invention, in a recording / reproducing apparatus for recording / reproducing a video digital signal, a means for measuring a frame cycle of an input video signal by a reference clock, and performing a good MPEG compression process in accordance with the cycle. A recording / reproducing apparatus comprising: bank control means for skipping or repeating a write bank of an MPEG compression processing memory.

In a fourth aspect based on the third aspect, the bank control means includes means for generating a detection window for detecting a vertical synchronization signal from the input video signal, and a vertical synchronization signal of the input video signal. A recording / reproducing apparatus comprising means for generating a complementary V-sync pulse at a position close to the position.

In a fifth aspect based on the third aspect, when the input video signal is a non-interlace signal, the bank control means determines the non-interlace signal from the V synchronization signal and the H synchronization signal to generate a determination pulse. And a means for judging that the external input signal is in a blank period from the number of generations of the complementary V synchronization pulse to generate a judgment pulse.

In a sixth aspect based on the third aspect, when the frame length of the input video signal is longer than a reference frame length, the bank control means exceeds a threshold period. In this case, the frame repetition information pulse (REPEA) for changing the value of the read control register of the frame memory of the MPEG encoding to the previous value.
T), and when the frame length of the input video signal is longer than a reference frame length within a certain threshold period, a pulse (REP_HLD pulse) having a period width longer than the threshold period is generated, and an external input signal is generated. When the frame length is shorter than the reference frame length, when the shorter length exceeds a certain threshold period, the value of the read control register of the frame memory of the MPEG coding is set to 1
A frame skip pulse (SKIP pulse) for changing the value to the next value is generated. If the frame length of the input video signal is shorter than a reference frame length within a certain threshold period, the period width shortened within the threshold period is used. (SKP_HLD pulse).

[0015]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of a video signal synchronizing method according to the present invention.

In FIG. 1, an S video signal or a composite signal is input as an external input. After this is subjected to analog processing such as synchronization separation and NTSC chroma decoding by the VIO circuit 1, the digital data (Y_e, C_
e). This digital data (Y, C) is M
The data is input to the PEG encoder circuit 3, subjected to MPEG encoding, and sent to an external medium. The horizontal synchronization signal (HD_e) synchronized and separated by the VIO circuit 1
x) and the vertical synchronizing signal (VD_ex) are input to the bank control signal generation circuit 2, and the horizontal synchronizing signal (HD_e) and the vertical synchronizing signal (VD_
e), which is input to the MPEG encoder circuit 3,
This is a control signal for the PEG encoding process. The TG (timing generator) 4 supplies the frame signal (FP_i) generated by the internal reference clock to the bank control signal generation circuit 2. It is also input to the MPEG encoder circuit 3 and becomes a control signal for MPEG encoding processing.

The bank control signal generation circuit 2 controls a bank of a frame memory 17 for performing an MPEG encoding process in accordance with a cycle of an external input signal, a frame skip signal (SKIP), and a frame repeat signal (REPAE).
T), a frame skip hold signal (SKP_HL)
D), a frame repeat hold signal (REP_HL)
D) is generated and sent to the CPU circuit 5. The CPU circuit 5 controls the control signals SKIP, REPET, SKP_HLD,
Based on the REP_HLD, the setting of the internal register is controlled so that the optimal MPEG encoding process is performed.

The operation of the MPEG encoder circuit 3 under the control of the bank control signal generation circuit 2 and the CPU circuit 5 is described below.
This will be described with reference to FIGS.

In both figures, for the sake of simplicity in the description, the periodic fluctuations are shown schematically with a greater period variation than the actual one. FIG. 2 shows R
FIG. 3 shows the state transition of the bank designation at the time of the EPEAT.
The operation at the time of the state transition of the bank designation at the time of P is shown, and FM0 to FM4 represent the banks of the frame memory 17.

In FIG. 2, an external input synchronization signal (Xps
When (t_e) becomes longer than the internal reference synchronization signal (Xpst_i) ((a) in FIG. 2), first, in order to prevent random occurrence of a repeat, a frame repeat hold signal (REP_HLD) indicating that a hold period is in progress is generated. . At this time,
The CUP circuit 5 writes the contents of "write bank (2)" to the "write bank" register for the repeat operation of the bank designation register. Also, since the length of the external input synchronization signal (Xpst_e) does not exceed a certain threshold period, the frame repeat signal (REPAE)
Since T) does not occur and the “read register” is not rewritten, normal encoding processing is performed by the MPEG encoder circuit 3.

Next, when the phase difference becomes equal to or less than 0 frame ((b) in FIG. 2), a frame repeat hold signal (REP_HLD) is generated as in (a). Since the length of the external input synchronizing signal (Xpst_e) exceeds a certain threshold period, a frame repeat signal (REPAET) is generated. At the same time, the internal repeat register “repeat (reg)” is enabled in the CPU circuit 5 and the “read bank” "Register to" F
M1 "to enter the repeat state. At this time, "FM2"
Since the writing to is skipped, it is preferentially written to "FM2". In this case, although one example, the read frame of I and P is set immediately before and the same frame is encoded as two B frames. This control is not limited to this, and a convenient bank designation may be performed depending on the system.

FIG. 3 shows a state transition of bank designation at the time of SKIP. When the external input synchronizing signal (Xpst_e) becomes shorter than the internal reference synchronizing signal (Xpst_i) ((c) in FIG. 3), first, a frame skip hold signal (SKP) indicating that a hold period is being performed to prevent skip occurrences.
_HLD). External input synchronization signal (Xpst_
e) Since the length does not exceed a certain threshold period, no frame skip signal (SKIP) is generated, and the "readout register" is not rewritten. Therefore, normal encoding processing is performed by the MPEG encoder circuit 3.

Subsequently, when the phase difference becomes one frame or more ((d) in FIG. 3), a frame skip hold signal (SKP_HLD) is generated as in (c). Since the length of the external input synchronizing signal (Xpst_e) exceeds a certain threshold period, a frame skip signal (SKIP) is generated. At the same time, the CPU circuit 5 enables the internal skip register “skip (reg)” and enables the “write bank”. "Is set to" FM1 "and a skip state is set. In this case, since two frames are only written in the same frame, the bank management is the same as the normal operation.

The MPEG bit stream subjected to the above control is recorded on a medium such as a hard disk or an optical disk. At the time of reproduction, MPE reproduced from a disc etc.
The G bit stream is input to the MPEG decoder 7 and is subjected to a predetermined decoding process to obtain the luminance digital data (Y
_I), converted to color difference digital data (C_i)
Output to the IO circuit 6. At the same time, the horizontal synchronization signal (HD_
i), and also outputs a vertical synchronization signal (VD_i) to the VIO circuit 6.

The VIO circuit 6 performs D / A (digital / analog) conversion of the luminance digital data (Y_i) and the chrominance digital data (C_i), and performs processing such as NTSC chroma encoding and synchronization addition.
Or output as a composite signal.

As described above, according to the present embodiment, the frame memory 17 for performing the MPEG encoding process is controlled without providing a separate frame memory for non-standard signals, so that a simple and low-cost non-standard signal can be used. Provided is a video synchronization method capable of standardizing a standard signal and performing a good MPEG encoding process, and a recording / reproducing apparatus incorporating the same.

Next, regarding the bank control signal generation circuit 2,
This will be described with reference to the more detailed configuration diagram of FIG. 4, the timing charts of FIGS. 5 and 6, and the state transition diagram of FIG.

Here, a means for measuring the length of a frame pulse synchronized with a vertical synchronization signal of an input video signal with a reference clock, and a method for preventing erroneous detection or loss of synchronization due to pseudo-synchronization generated by noise or the like. A means for generating a detection window and not detecting a vertical synchronization signal other than the specified period ± α, a means for generating interpolation synchronization as a measure against synchronization loss when there is no synchronization signal in the detection window, If there is a significant change in the frame length, this is automatically determined and the detection window is opened to detect the synchronization signal of the external input signal as it is. If there is, M
Means for generating interpolation synchronization for compensating for erasure synchronization in order to complete PEG processing. Means for simulating the judgment of even and odd fields when a signal input from the outside is a non-interlace signal. If the frame length of the external input is shorter than the frame length, an arbitrary threshold value is provided to prevent detection from being generated in the vicinity of the boundary, and if the threshold value is set during that period, a hold is performed. , If the length of the external input frame length is greater than a certain hold period value, the MPE
A means for generating a pulse for controlling reading of the memory for G-encoding processing, and an arbitrary threshold value provided to prevent random occurrence of detection near the boundary when the frame length of the external input is longer than the reference frame length. Means for generating a pulse during the hold period, and a pulse for controlling writing and reading of the MPEG encoding processing memory when the external input frame length is longer than a certain hold period value. Including one or more of means for generating
It can flexibly respond to sudden error input (non-interlace signal or blank signal).

In FIG. 4, an external input synchronization signal (Xps
t_e) is input to the frame period measuring circuit 8, and its period is measured by the internal reference clock. From the measurement result, if the frame period of the external input synchronization signal (Xpst_e) is longer than the standard frame period, LONG_P is generated, and if shorter, SHORT_P is generated. This is sent to the repeat / skip pulse generation circuit 13. In addition, the frame period measurement circuit 8 determines that the frame period of the external input synchronization signal (Xpst_e) is extremely larger than the standard frame period (± 3% to ± 7%).
%), It is determined to be search reproduction or the like, and SCH_P is generated. This is called the V detection window generation circuit 1
Send to 0.

The V detection window generation circuit 10 generates a detection window having a certain width with respect to the V synchronization position predicted so as not to malfunction due to the pseudo synchronization signal. This detection window is expanded when SCH_P from the frame period measurement circuit 8 is enabled,
It operates to ensure V synchronization of the external input signal. The detection window controlled in this way is sent to the V detection circuit 9. The V detection circuit 9 detects only the V synchronization within the detection window, and generates a complementary V synchronization when there is no V synchronization within the detection window, and generates the V synchronization signal (VD_e) of the external input signal as an MPEG encoder circuit. Supply to 3.

When the external input signal is a non-interlace signal, the non-inter detection circuit 11 detects
Generates _ERR. This is supplied to the frame pulse generation circuit 14. The blank detection circuit 12 outputs the signal BLANK during the blanking period when the signal is lost due to the splicing shooting with the VTR.
Is generated and supplied to the frame pulse generation circuit 14.

The frame pulse generation circuit 14 generates a frame start pulse (FP_e) even for a sudden error based on the protected V synchronization signal (VD_e), INT_ERR for which non-interlace determination has been performed, and BLANK indicating a blank period. And supplies a frame start pulse (FP_e) to the MPEG encoder 3 stably.

When Xpst_e is longer than the standard frame period Xpst_i, when the repeat / skip pulse generation circuit 13 is longer than a certain threshold width as shown in FIG.
Generate REP_HLD, REPEAT if more
Generate Also, the frame period of Xpst_e is Xps
In the case of being shorter than t_i, SKI_HLD is generated when it is shorter than a certain threshold width as shown in FIG. 6, and SKIP is generated when it is longer than t_i.

The operation will be further described with reference to a state transition diagram and FIG.

The state is Xpst_i = '0', Xpst_
It is determined in the order of occurrence of e = '0'. Xpst_i =
If '0' is repeated twice, a hysteresis period of REPEAT occurs, and Xps reaches a predetermined width (threshold width).
When t_e = '0', the state returns to the NORMAL state, and when the hysteresis period exceeds a predetermined width (threshold width), the state becomes the REPET state. When Xpst_e is repeated twice, a hysteresis period of SKIP occurs. When Xpst_i becomes “0” by a predetermined width (threshold width), the state returns to the NORMAL state. Become. In a state other than NORMAL1 and NORMAL2, the same signal as the state name becomes "1". If conditions for the state transition occur simultaneously, the transition is (priority).
The threshold width is arbitrarily given by a register. The state transition of bank designation is shown as an example based on the control signal.

[0037]

As described above, according to the present invention, a non-standard signal can be converted into a standard signal by controlling a bank of a frame memory for performing the MPEG encoding process by an appropriate control pulse without providing a separate frame memory. As a result, good MPEG encoding processing can be performed, and cost reduction can be expected. It can also respond flexibly to sudden error inputs (non-interlace signals or blank signals).

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing an embodiment of the present invention.

FIG. 2 is a timing chart when bank control is repeated in one embodiment.

FIG. 3 is a timing chart when a bank control jump occurs according to the embodiment;

FIG. 4 is a configuration diagram showing a detailed internal example of a bank control signal generation unit according to one embodiment;

FIG. 5 is a timing chart illustrating a repetitive operation in one embodiment.

FIG. 6 is a timing chart illustrating a jump operation in one embodiment.

FIG. 7 shows a repetition (REPEA) in one embodiment.
T) is a state transition diagram illustrating the occurrence of skip (SKIP).

FIG. 8 is a timing chart illustrating a repetitive operation in a conventional frame synchronizer.

FIG. 9 is a timing chart illustrating a jump operation in a conventional frame synchronizer.

FIG. 10 is a configuration diagram of a conventional frame synchronizer.

[Explanation of symbols]

 Reference Signs List 1 video input / output circuit 2 bank control signal generation circuit 3 MPEG encoder circuit 4 timing generator 5 CPU 8 frame period measurement circuit 9 V synchronization detection circuit 10 detection window generation circuit 11 non-interlace signal detection circuit 12 blank signal detection circuit 13 repeat / Skip pulse generation circuit 14 Frame pulse generation circuit 15 External input signal frame pulse generation circuit 16 H synchronization protection circuit 17 Frame memory

Continued on the front page F-term (reference) 5C053 FA22 GA11 GB10 GB37 JA28 KA03 KA18 5C059 KK08 PP04 SS14 TA71 TB04 TC21 TD11 UA02 UA09 UA34 5D044 AB07 EF03 FG10 GK03 GK08 HL11

Claims (6)

[Claims] In a recording / reproducing apparatus for recording / reproducing a video digital signal, a frame cycle of an input video signal is measured with a reference clock, and writing to an MPEG compression processing memory for performing a good MPEG compression process according to the cycle is performed. A video synchronization method comprising synchronizing an input video signal to an internal system of the recording / reproducing apparatus by skipping or repeating a bank. 2. If the frame period of the input video signal is longer than a reference frame period by a specified range or more, MPEG
The reading of the frame bank of the compression processing memory is repeated, and the reading of the frame bank of the MPEG compression processing memory is skipped when the frame period of the input video signal is shorter than a reference frame period by a specified range or more. The video synchronization method according to claim 1. 3. A recording / reproducing apparatus for recording / reproducing a video digital signal, means for measuring a frame cycle of an input video signal with a reference clock, and an MPEG compression processing memory for performing a good MPEG compression process according to the cycle. And a bank control means for skipping or repeating the write bank of the recording / reproducing apparatus. 4. The bank control means includes means for generating a detection window for detecting a vertical synchronization signal from the input video signal, and a complementary V synchronization pulse at a position close to a vertical synchronization signal position of the input video signal. 4. The recording / reproducing apparatus according to claim 3, further comprising: means for generating. 5. When the input video signal is a non-interlace signal, the bank control means determines the V-sync signal from the V-sync signal and the H-sync signal to generate a determination pulse. 4. The recording / reproducing apparatus according to claim 3, further comprising means for judging the existence from the number of generations of the complementary V synchronization pulse and generating a judgment pulse. 6. The bank control means, if the frame length of the input video signal is longer than a reference frame length, if the length exceeds a certain threshold period, MPEG
A frame repetition information pulse (REPEAT pulse) for changing the value of the read control register of the encoding frame memory to the previous value is generated, and the frame length of the input video signal is within a certain threshold period from the reference frame length. When the frame length of the external input signal is shorter than the reference frame length, the pulse exceeds the threshold period when the frame length of the external input signal is shorter than the reference frame length. In this case, a frame skip pulse (SKIP pulse) for changing the value of the read control register of the frame memory of the MPEG encoding to the next value is generated, and the threshold of the frame length of the input video signal is larger than the reference frame length. If it is short within the period, it will be shorter than the period width within the threshold period. Luz (SKP_HLD pulse) recording and reproducing apparatus according to claim 3, wherein the generating.